aboutsummaryrefslogtreecommitdiff
path: root/arch/sh/boards/superh
diff options
context:
space:
mode:
authorSimon Arlott <simon@fire.lp0.eu>2007-05-14 08:15:10 +0900
committerPaul Mundt <lethal@linux-sh.org>2007-05-21 14:31:39 +0900
commite868d61272caa648214046a096e5a6bfc068dc8c (patch)
tree087153c10725af12129ac8c55bda489f255bdd2c /arch/sh/boards/superh
parent049fa57ce3b22d9f5acb251070941b630ee71d6e (diff)
spelling fixes: arch/sh/
Spelling fixes in arch/sh/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards/superh')
-rw-r--r--arch/sh/boards/superh/microdev/io.c6
-rw-r--r--arch/sh/boards/superh/microdev/irq.c6
-rw-r--r--arch/sh/boards/superh/microdev/setup.c2
3 files changed, 7 insertions, 7 deletions
diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/superh/microdev/io.c
index 83419bf4c83..b704e20d7e4 100644
--- a/arch/sh/boards/superh/microdev/io.c
+++ b/arch/sh/boards/superh/microdev/io.c
@@ -198,12 +198,12 @@ void microdev_outb(unsigned char b, unsigned long port)
/*
* There is a board feature with the current SH4-202 MicroDev in
* that the 2 byte enables (nBE0 and nBE1) are tied together (and
- * to the Chip Select Line (Ethernet_CS)). Due to this conectivity,
+ * to the Chip Select Line (Ethernet_CS)). Due to this connectivity,
* it is not possible to safely perform 8-bit writes to the
* Ethernet registers, as 16-bits will be consumed from the Data
* lines (corrupting the other byte). Hence, this function is
- * written to impliment 16-bit read/modify/write for all byte-wide
- * acceses.
+ * written to implement 16-bit read/modify/write for all byte-wide
+ * accesses.
*
* Note: there is no problem with byte READS (even or odd).
*
diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/superh/microdev/irq.c
index 8c64baa3036..cc1cb04fa61 100644
--- a/arch/sh/boards/superh/microdev/irq.c
+++ b/arch/sh/boards/superh/microdev/irq.c
@@ -100,7 +100,7 @@ static void disable_microdev_irq(unsigned int irq)
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
- /* disable interupts on the FPGA INTC register */
+ /* disable interrupts on the FPGA INTC register */
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
}
@@ -125,7 +125,7 @@ static void enable_microdev_irq(unsigned int irq)
priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
ctrl_outl(priorities, priorityReg);
- /* enable interupts on the FPGA INTC register */
+ /* enable interrupts on the FPGA INTC register */
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
}
@@ -152,7 +152,7 @@ extern void __init init_microdev_irq(void)
{
int i;
- /* disable interupts on the FPGA INTC register */
+ /* disable interrupts on the FPGA INTC register */
ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c
index 031c814e6e7..6396cea1c89 100644
--- a/arch/sh/boards/superh/microdev/setup.c
+++ b/arch/sh/boards/superh/microdev/setup.c
@@ -349,7 +349,7 @@ static int __init smsc_superio_setup(void)
SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
- /* Exit the configuraton state */
+ /* Exit the configuration state */
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
return 0;