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authorPaul Mundt <lethal@linux-sh.org>2009-03-11 16:12:39 +0900
committerPaul Mundt <lethal@linux-sh.org>2009-04-16 16:00:15 +0900
commit3aabce8d3d2f9af2c08c2f590ac9acb272ca8c95 (patch)
tree951cb912d729b04c102f3bea28a56bfb64db66d3 /arch/sh/drivers/pci/fixups-sh7785lcr.c
parent10591578c84825a320734e59272f161385edcc41 (diff)
sh: sh7785lcr: Update for recent PCI changes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/fixups-sh7785lcr.c')
-rw-r--r--arch/sh/drivers/pci/fixups-sh7785lcr.c33
1 files changed, 17 insertions, 16 deletions
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
index 4949e601387..9e7dc79037e 100644
--- a/arch/sh/drivers/pci/fixups-sh7785lcr.c
+++ b/arch/sh/drivers/pci/fixups-sh7785lcr.c
@@ -15,32 +15,33 @@
#include <linux/pci.h>
#include "pci-sh4.h"
-int pci_fixup_pcic(void)
+int pci_fixup_pcic(struct pci_channel *chan)
{
- pci_write_reg(0x000043ff, SH4_PCIINTM);
- pci_write_reg(0x0000380f, SH4_PCIAINTM);
+ pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
+ pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
- pci_write_reg(0xfbb00047, SH7780_PCICMD);
- pci_write_reg(0x00000000, SH7780_PCIIBAR);
+ pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);
+ pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
- pci_write_reg(0x00011912, SH7780_PCISVID);
- pci_write_reg(0x08000000, SH7780_PCICSCR0);
- pci_write_reg(0x0000001b, SH7780_PCICSAR0);
- pci_write_reg(0xfd000000, SH7780_PCICSCR1);
- pci_write_reg(0x0000000f, SH7780_PCICSAR1);
+ pci_write_reg(chan, 0x00011912, SH7780_PCISVID);
+ pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
+ pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
+ pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
+ pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
- pci_write_reg(0xfd000000, SH7780_PCIMBR0);
- pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
+ pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
+ pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
#ifdef CONFIG_32BIT
- pci_write_reg(0xc0000000, SH7780_PCIMBR2);
- pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
+ pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
+ pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
#endif
/* Set IOBR for windows containing area specified in pci.h */
- pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
+ pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE - 1),
SH7780_PCIIOBR);
- pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
+ pci_write_reg(chan, ((SH7780_PCI_IO_SIZE - 1) & (7 << 18)),
+ SH7780_PCIIOBMR);
return 0;
}