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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-15 10:01:15 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-15 10:01:15 -0800 |
| commit | f99c6bb6e2e9c35bd3dc0b1d0faa28bd6970930d (patch) | |
| tree | 338721c5084d536208a944567c2dface6a38a994 /arch/sh/mm/ioremap.c | |
| parent | e0a04cffa4e97e1e53625e40e70895c882e8972f (diff) | |
| parent | 9c57548f17806ffd8e4dc4f7973ce78bbfbc2079 (diff) | |
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (35 commits)
sh: rts7751r2d board updates.
sh: Kill off dead bigsur and ec3104 boards.
sh: Fixup r7780rp pata_platform for devres conversion.
sh: Revert TLB miss fast-path changes that broke PTEA parts.
sh: Compile fix for heartbeat consolidation.
sh: heartbeat consolidation for banked LEDs.
sh: define dma noncoherent API functions.
sh: Missing flush_dcache_all() proto in cacheflush.h.
sh: Kill dead/unused ISA code from __ioremap().
sh: Add cpu-features header to asm/Kbuild.
sh: Move __KERNEL__ up in asm/page.h.
sh: Fix syscall numbering breakage.
sh: dcache write-back for R7780RP PIO.
sh: Switch to local TLB flush variants in additional callsites.
sh: Local TLB flushing variants for SMP prep.
sh: Fixup cpu_data references for the non-boot CPUs.
sh: Use a per-cpu ASID cache.
sh: add SH_CLK_MD Kconfig default.
sh: Fixup SHMIN INTC register definitions.
sh: SH-DMAC compile fixes
...
Diffstat (limited to 'arch/sh/mm/ioremap.c')
| -rw-r--r-- | arch/sh/mm/ioremap.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/sh/mm/ioremap.c b/arch/sh/mm/ioremap.c index 90b494a0cf4..be03d74e99c 100644 --- a/arch/sh/mm/ioremap.c +++ b/arch/sh/mm/ioremap.c @@ -45,12 +45,6 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size, return NULL; /* - * Don't remap the low PCI/ISA area, it's always mapped.. - */ - if (phys_addr >= 0xA0000 && last_addr < 0x100000) - return (void __iomem *)phys_to_virt(phys_addr); - - /* * If we're on an SH7751 or SH7780 PCI controller, PCI memory is * mapped at the end of the address space (typically 0xfd000000) * in a non-translatable area, so mapping through page tables for |