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authorIngo Molnar <mingo@elte.hu>2008-02-26 08:52:33 +0100
committerIngo Molnar <mingo@elte.hu>2008-04-17 17:40:51 +0200
commitd0e95ebdc5cf5fe6fa29f2e0a5c6a0fe5c5aa50f (patch)
treec07b4afb14fb557920bb6f2994e967c5fd6dab9e /arch/x86/kernel/cpu
parent1d007cd5aeea2c9283e01433dbce4c9f91dd7823 (diff)
x86: clean up cpu capabilities in arch/x86/kernel/cpu/intel.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/intel.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index c9ecf378cc4..fe9224c51d3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -143,12 +143,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
unsigned eax = cpuid_eax(10);
/* Check for version and the number of counters */
if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
- set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
}
/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
- clear_bit(X86_FEATURE_SEP, c->x86_capability);
+ clear_cpu_cap(c, X86_FEATURE_SEP);
/*
* Names for the Pentium II/Celeron processors
@@ -209,19 +209,19 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
#endif
if (cpu_has_xmm2)
- set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
if (c->x86 == 15) {
- set_bit(X86_FEATURE_P4, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_P4);
}
if (c->x86 == 6)
- set_bit(X86_FEATURE_P3, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_P3);
if (cpu_has_ds) {
unsigned int l1;
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<11)))
- set_bit(X86_FEATURE_BTS, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_BTS);
if (!(l1 & (1<<12)))
- set_bit(X86_FEATURE_PEBS, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_PEBS);
}
if (cpu_has_bts)