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authorYinghai Lu <yhlu.kernel@gmail.com>2008-07-13 14:30:35 -0700
committerIngo Molnar <mingo@elte.hu>2008-07-14 09:24:16 +0200
commit87a1c441e1aeaf00f97e63dfc310ea7684ec9dda (patch)
tree0fb5840a55d833cb0be7f000e8c85e02ff1f5336 /arch/x86/kernel
parent32b23e9a7331fce57eb0af52e19e8409fdef831b (diff)
x86: get x86_phys_bits early
when try to make hpet_enable use io_remap instead fixmap got ioremap: invalid physical address fed00000 ------------[ cut here ]------------ WARNING: at arch/x86/mm/ioremap.c:161 __ioremap_caller+0x8c/0x2f3() Modules linked in: Pid: 0, comm: swapper Not tainted 2.6.26-rc9-tip-01873-ga9827e7-dirty #358 Call Trace: [<ffffffff8026615e>] warn_on_slowpath+0x6c/0xa7 [<ffffffff802e2313>] ? __slab_alloc+0x20a/0x3fb [<ffffffff802d85c5>] ? mpol_new+0x88/0x17d [<ffffffff8022a4f4>] ? mcount_call+0x5/0x31 [<ffffffff8022a4f4>] ? mcount_call+0x5/0x31 [<ffffffff8024b0d2>] __ioremap_caller+0x8c/0x2f3 [<ffffffff80e86dbd>] ? hpet_enable+0x39/0x241 [<ffffffff8022a4f4>] ? mcount_call+0x5/0x31 [<ffffffff8024b466>] ioremap_nocache+0x2a/0x40 [<ffffffff80e86dbd>] hpet_enable+0x39/0x241 [<ffffffff80e7a1f6>] hpet_time_init+0x21/0x4e [<ffffffff80e730e9>] start_kernel+0x302/0x395 [<ffffffff80e722aa>] x86_64_start_reservations+0xb9/0xd4 [<ffffffff80e722fe>] ? x86_64_init_pda+0x39/0x4f [<ffffffff80e72400>] x86_64_start_kernel+0xec/0x107 ---[ end trace a7919e7f17c0a725 ]--- it seems for amd system that is set later... try to move setting early in early_identify_cpu. and remove same code for intel and centaur. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/cpu/centaur_64.c10
-rw-r--r--arch/x86/kernel/cpu/common_64.c14
-rw-r--r--arch/x86/kernel/cpu/intel_64.c10
3 files changed, 8 insertions, 26 deletions
diff --git a/arch/x86/kernel/cpu/centaur_64.c b/arch/x86/kernel/cpu/centaur_64.c
index 2026d2119cd..1d181c40e2e 100644
--- a/arch/x86/kernel/cpu/centaur_64.c
+++ b/arch/x86/kernel/cpu/centaur_64.c
@@ -16,16 +16,6 @@ static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
{
- /* Cache sizes */
- unsigned n;
-
- n = c->extended_cpuid_level;
- if (n >= 0x80000008) {
- unsigned eax = cpuid_eax(0x80000008);
- c->x86_virt_bits = (eax >> 8) & 0xff;
- c->x86_phys_bits = eax & 0xff;
- }
-
if (c->x86 == 0x6 && c->x86_model >= 0xf) {
c->x86_cache_alignment = c->x86_clflush_size * 2;
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
index 36537ab9e56..7b8cc72feb4 100644
--- a/arch/x86/kernel/cpu/common_64.c
+++ b/arch/x86/kernel/cpu/common_64.c
@@ -98,7 +98,7 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
{
- unsigned int n, dummy, eax, ebx, ecx, edx;
+ unsigned int n, dummy, ebx, ecx, edx;
n = c->extended_cpuid_level;
@@ -121,11 +121,6 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
c->x86_cache_size, ecx & 0xFF);
}
- if (n >= 0x80000008) {
- cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
- c->x86_virt_bits = (eax >> 8) & 0xff;
- c->x86_phys_bits = eax & 0xff;
- }
}
void __cpuinit detect_ht(struct cpuinfo_x86 *c)
@@ -314,6 +309,13 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
if (c->extended_cpuid_level >= 0x80000007)
c->x86_power = cpuid_edx(0x80000007);
+ if (c->extended_cpuid_level >= 0x80000008) {
+ u32 eax = cpuid_eax(0x80000008);
+
+ c->x86_virt_bits = (eax >> 8) & 0xff;
+ c->x86_phys_bits = eax & 0xff;
+ }
+
/* Assume all 64-bit CPUs support 32-bit syscall */
set_cpu_cap(c, X86_FEATURE_SYSCALL32);
diff --git a/arch/x86/kernel/cpu/intel_64.c b/arch/x86/kernel/cpu/intel_64.c
index 02f773399e3..1019c58d39f 100644
--- a/arch/x86/kernel/cpu/intel_64.c
+++ b/arch/x86/kernel/cpu/intel_64.c
@@ -54,9 +54,6 @@ static void __cpuinit srat_detect_node(void)
static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
- /* Cache sizes */
- unsigned n;
-
init_intel_cacheinfo(c);
if (c->cpuid_level > 9) {
unsigned eax = cpuid_eax(10);
@@ -78,13 +75,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
if (cpu_has_bts)
ds_init_intel(c);
- n = c->extended_cpuid_level;
- if (n >= 0x80000008) {
- unsigned eax = cpuid_eax(0x80000008);
- c->x86_virt_bits = (eax >> 8) & 0xff;
- c->x86_phys_bits = eax & 0xff;
- }
-
if (c->x86 == 15)
c->x86_cache_alignment = c->x86_clflush_size * 2;
if (c->x86 == 6)