diff options
| author | Andi Kleen <ak@suse.de> | 2006-01-11 22:42:45 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-11 19:01:12 -0800 |
| commit | 39b3a7910556005a7a0d042ecb7ff98bfa84ea57 (patch) | |
| tree | efcb2602e6fd198c9af34e726741eb389fa4e292 /arch/x86_64 | |
| parent | 2d52ede9876ba566b583f255fdc43800eea81baa (diff) | |
[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag
Define it for i386 too.
This is a synthetic flag that signifies that the CPU's TSC runs
at a constant P state invariant frequency.
Fix up the logic on x86-64/i386 to set it on all known CPUs.
Use the AMD defined bit to set it on future AMD CPUs.
Cc: venkatesh.pallipadi@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64')
| -rw-r--r-- | arch/x86_64/kernel/setup.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c index 754a05f9b4d..d9c1c3bd615 100644 --- a/arch/x86_64/kernel/setup.c +++ b/arch/x86_64/kernel/setup.c @@ -1032,7 +1032,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) if (c->x86 == 15) c->x86_cache_alignment = c->x86_clflush_size * 2; - if (c->x86 >= 15) + if ((c->x86 == 0xf && c->x86_model >= 0x03) || + (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); c->x86_max_cores = intel_num_cpu_cores(c); @@ -1273,7 +1274,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) "tm", "stc" "?", - "constant_tsc", + /* nothing */ /* constant_tsc - moved to flags */ }; |