diff options
| author | Chris Zankel <chris@zankel.net> | 2007-05-31 17:49:32 -0700 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2007-05-31 17:49:32 -0700 |
| commit | 29c4dfd92edc26c2cd2c0c64c9201d5b91d6418e (patch) | |
| tree | 64b2884bb49a86f2895d9206b79bf9f64e384615 /arch/xtensa/kernel/entry.S | |
| parent | adba09f01577ea441a761a85aacb1e43b58d35c4 (diff) | |
[XTENSA] Remove non-rt signal handling
The non-rt signal handling was never really used, so we don't break
anything. This patch also cleans up the signal stack-frame to make
it independent from the processor configuration. It also improves
the method used for controlling single-stepping. We now save and
restore the 'icountlevel' register that controls single stepping
and set or clear the saved state to enable or disable it.
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/kernel/entry.S')
| -rw-r--r-- | arch/xtensa/kernel/entry.S | 36 |
1 files changed, 14 insertions, 22 deletions
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index 9e271ba009b..8dc7a2c26ff 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -125,8 +125,9 @@ _user_exception: movi a2, 0 rsr a3, SAR - wsr a2, ICOUNTLEVEL + xsr a2, ICOUNTLEVEL s32i a3, a1, PT_SAR + s32i a2, a1, PT_ICOUNTLEVEL /* Rotate ws so that the current windowbase is at bit0. */ /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ @@ -276,8 +277,9 @@ _kernel_exception: movi a2, 0 rsr a3, SAR - wsr a2, ICOUNTLEVEL + xsr a2, ICOUNTLEVEL s32i a3, a1, PT_SAR + s32i a2, a1, PT_ICOUNTLEVEL /* Rotate ws so that the current windowbase is at bit0. */ /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ @@ -330,14 +332,16 @@ _kernel_exception: common_exception: - /* Save EXCVADDR, DEBUGCAUSE, and PC, and clear LCOUNT */ + /* Save some registers, disable loops and clear the syscall flag. */ rsr a2, DEBUGCAUSE rsr a3, EPC_1 s32i a2, a1, PT_DEBUGCAUSE s32i a3, a1, PT_PC + movi a2, -1 rsr a3, EXCVADDR + s32i a2, a1, PT_SYSCALL movi a2, 0 s32i a3, a1, PT_EXCVADDR xsr a2, LCOUNT @@ -450,27 +454,8 @@ common_exception_return: /* Restore the state of the task and return from the exception. */ - - /* If we are returning from a user exception, and the process - * to run next has PT_SINGLESTEP set, we want to setup - * ICOUNT and ICOUNTLEVEL to step one instruction. - * PT_SINGLESTEP is set by sys_ptrace (ptrace.c) - */ - 4: /* a2 holds GET_CURRENT(a2,a1) */ - l32i a3, a2, TI_TASK - l32i a3, a3, TASK_PTRACE - bbci.l a3, PT_SINGLESTEP_BIT, 1f # jump if single-step flag is not set - - movi a3, -2 # PT_SINGLESTEP flag is set, - movi a4, 1 # icountlevel of 1 means it won't - wsr a3, ICOUNT # start counting until after rfe - wsr a4, ICOUNTLEVEL # so setup icount & icountlevel. - isync - -1: - #if XCHAL_EXTRA_SA_SIZE /* For user exceptions, restore the extra state from the user's TCB. */ @@ -665,6 +650,13 @@ common_exception_exit: wsr a3, LEND wsr a2, LCOUNT + /* We control single stepping through the ICOUNTLEVEL register. */ + + l32i a2, a1, PT_ICOUNTLEVEL + movi a3, -2 + wsr a2, ICOUNTLEVEL + wsr a3, ICOUNT + /* Check if it was double exception. */ l32i a0, a1, PT_DEPC |