S3C64XX: Add DVFS support to the S3C64XX cpufreq driver

Use the regulator framework to provide optional support for DVFS in
the S3C64XX cpufreq driver. When a software controllable regulator
is configured the driver will use it to lower the supply voltage when
running at a lower frequency, giving improved power saving.

When regulator support is disabled or no regulator can be obtained
for VDDARM the driver will fall back to scaling only the frequency.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

1 files changed, 91 insertions, 18 deletions

diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index 4179cab3dfb..97617e54bd5 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -15,26 +15,42 @@
 #include <linux/cpufreq.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/cpu.h>
 
 static struct clk *armclk;
+static struct regulator *vddarm;
+
+struct s3c64xx_dvfs {
+	unsigned int vddarm_min;
+	unsigned int vddarm_max;
+};
+
+static struct s3c64xx_dvfs s3c6410_dvfs_table[] = {
+	[0] = { 1000000, 1000000 },
+	[1] = { 1000000, 1050000 },
+	[2] = { 1050000, 1100000 },
+	[3] = { 1050000, 1150000 },
+	[4] = { 1250000, 1350000 },
+};
 
 static struct cpufreq_frequency_table s3c6410_freq_table[] = {
 	{ 0,  66000 },
-	{ 1, 133000 },
-	{ 2, 222000 },
-	{ 3, 266000 },
-	{ 4, 333000 },
-	{ 5, 400000 },
-	{ 6, 532000 },
-	{ 7, 533000 },
-	{ 8, 667000 },
+	{ 0, 133000 },
+	{ 1, 222000 },
+	{ 1, 266000 },
+	{ 2, 333000 },
+	{ 2, 400000 },
+	{ 3, 532000 },
+	{ 3, 533000 },
+	{ 4, 667000 },
 	{ 0, CPUFREQ_TABLE_END },
 };
 
 /* Data tables for current CPU and maximum index into it */
 static struct cpufreq_frequency_table *s3c64xx_freq_table;
+static struct s3c64xx_dvfs *s3c64xx_dvfs_table;
 
 static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
 {
@@ -56,19 +72,21 @@ static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
 				      unsigned int target_freq,
 				      unsigned int relation)
 {
-	int ret;
-	unsigned int index;
+	int ret = 0;
+	unsigned int i;
 	struct cpufreq_freqs freqs;
+	struct s3c64xx_dvfs *dvfs;
 
 	ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
-					     target_freq, relation, &index);
+					     target_freq, relation, &i);
 	if (ret != 0)
 		return ret;
 
 	freqs.cpu = 0;
 	freqs.old = clk_get_rate(armclk) / 1000;
-	freqs.new = s3c64xx_freq_table[index].frequency;
+	freqs.new = s3c64xx_freq_table[i].frequency;
 	freqs.flags = 0;
+	dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
 
 	if (freqs.old == freqs.new)
 		return 0;
@@ -77,31 +95,68 @@ static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
 
 	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 
-	ret = clk_set_rate(armclk, freqs.new * 1000);
-
-	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+#ifdef CONFIG_REGULATOR
+	if (vddarm && freqs.new > freqs.old) {
+		ret = regulator_set_voltage(vddarm,
+					    dvfs->vddarm_min,
+					    dvfs->vddarm_max);
+		if (ret != 0) {
+			pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+			       freqs.new, ret);
+			goto err;
+		}
+	}
+#endif
 
+	ret = clk_set_rate(armclk, freqs.new * 1000);
 	if (ret < 0) {
 		pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
 		       freqs.new, ret);
-		return ret;
+		goto err;
+	}
+
+#ifdef CONFIG_REGULATOR
+	if (vddarm && freqs.new < freqs.old) {
+		ret = regulator_set_voltage(vddarm,
+					    dvfs->vddarm_min,
+					    dvfs->vddarm_max);
+		if (ret != 0) {
+			pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+			       freqs.new, ret);
+			goto err_clk;
+		}
 	}
+#endif
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 
 	pr_debug("cpufreq: Set actual frequency %lukHz\n",
 		 clk_get_rate(armclk) / 1000);
 
 	return 0;
+
+err_clk:
+	if (clk_set_rate(armclk, freqs.old * 1000) < 0)
+		pr_err("Failed to restore original clock rate\n");
+err:
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+	return ret;
 }
 
+
 static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 {
+	int ret;
 	struct cpufreq_frequency_table *freq;;
 
 	if (policy->cpu != 0)
 		return -EINVAL;
 
-	if (cpu_is_s3c6410())
+	if (cpu_is_s3c6410()) {
 		s3c64xx_freq_table = s3c6410_freq_table;
+		s3c64xx_dvfs_table = s3c6410_dvfs_table;
+	}
 
 	if (s3c64xx_freq_table == NULL) {
 		pr_err("cpufreq: No frequency information for this CPU\n");
@@ -115,6 +170,16 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 		return PTR_ERR(armclk);
 	}
 
+#ifdef CONFIG_REGULATOR
+	vddarm = regulator_get(NULL, "vddarm");
+	if (IS_ERR(vddarm)) {
+		ret = PTR_ERR(vddarm);
+		pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
+		pr_err("cpufreq: Only frequency scaling available\n");
+		vddarm = NULL;
+	}
+#endif
+
 	/* Check for frequencies we can generate */
 	freq = s3c64xx_freq_table;
 	while (freq->frequency != CPUFREQ_TABLE_END) {
@@ -132,7 +197,15 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 	policy->cur = clk_get_rate(armclk) / 1000;
 	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 
-	return cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
+	ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
+	if (ret == 0)
+		return ret;
+
+	pr_err("cpufreq: Failed to configure frequency table: %d\n", ret);
+
+	regulator_put(vddarm);
+	clk_put(armclk);
+	return ret;
 }
 
 static struct cpufreq_driver s3c64xx_cpufreq_driver = {