diff options
| author | Stuart Menefy <stuart.menefy@st.com> | 2009-08-24 18:27:33 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-24 18:27:33 +0900 |
| commit | 6000fc4d6f3e55ad52cce8d76317187fe01af2aa (patch) | |
| tree | bc86a1f13465a791b7e77f7663280bcb23fdd378 /arch | |
| parent | bd4fb4d4c1e4a5a2ffbf57a83817a749df1339dd (diff) | |
sh: Fixes some write posting issues in the interrupt handling for SH
It is possible for the CPU to re-enable it's interrupt block bit
before the write to the interrupt controller has actually masked out
the external interupt at the controller. We get around this by
reading back from the interrupt controller which will ensure the
write has happened.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sh/kernel/cpu/irq/ipr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 808d99a48ef..c1508a90fc6 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c @@ -35,6 +35,7 @@ static void disable_ipr_irq(unsigned int irq) unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set the priority in IPR to 0 */ __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr); + (void)__raw_readw(addr); /* Read back to flush write posting */ } static void enable_ipr_irq(unsigned int irq) |