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authorBen Dooks <ben@simtec.co.uk>2009-02-25 00:41:17 +0000
committerAndy Green <agreen@octopus.localdomain>2009-02-25 00:41:17 +0000
commit6972d14fb604e3065189686476ecc01f9d1f22d9 (patch)
treef2418e23b0a84a4d7ea5cd25ccbeaf75de94355d /arch
parent05225d2426dd3cf614a642741fe7f0c5ad7702fa (diff)
S3C64XX: Add DMA/SDMA clock sources
Add the clock sources for the DMA and SDMA controllers and ensure that they are shut down at startup. The DMA engines are dma0 and dma1, whilst the SDMA are called dma2 and dma3. Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-s3c64xx/clock.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index 136c982c68e..b12fc8ad217 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -152,6 +152,30 @@ static struct clk init_clocks_disable[] = {
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
+ }, {
+ .name = "dma0",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_DMA0,
+ }, {
+ .name = "dma1",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_DMA1,
+ }, {
+ .name = "dma2",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_SDMA0,
+ }, {
+ .name = "dma3",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_SDMA1,
},
};