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authorGraf Yang <graf.yang@analog.com>2008-04-24 04:43:14 +0800
committerBryan Wu <cooloney@kernel.org>2008-04-24 04:43:14 +0800
commit6ed839423073251b513664fdadb180634aed704b (patch)
tree073350299070ba091f4fb4fb146b9a931edc44b8 /arch
parentdb68254f0639a357309f02cf8707490265fa7a31 (diff)
[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.
Signed-off-by: Graf Yang <graf.yang@analog.com> Cc: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c16
-rw-r--r--arch/blackfin/mach-bf533/head.S16
-rw-r--r--arch/blackfin/mach-bf537/head.S16
-rw-r--r--arch/blackfin/mach-bf561/head.S16
4 files changed, 32 insertions, 32 deletions
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 7e8ceea9b5d..72477c252a9 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -95,14 +95,14 @@ enum {
AWA_data_clear = SYSCR,
AWA_data_set = SYSCR,
AWA_toggle = SYSCR,
- AWA_maska = UART_SCR,
- AWA_maska_clear = UART_SCR,
- AWA_maska_set = UART_SCR,
- AWA_maska_toggle = UART_SCR,
- AWA_maskb = UART_GCTL,
- AWA_maskb_clear = UART_GCTL,
- AWA_maskb_set = UART_GCTL,
- AWA_maskb_toggle = UART_GCTL,
+ AWA_maska = BFIN_UART_SCR,
+ AWA_maska_clear = BFIN_UART_SCR,
+ AWA_maska_set = BFIN_UART_SCR,
+ AWA_maska_toggle = BFIN_UART_SCR,
+ AWA_maskb = BFIN_UART_GCTL,
+ AWA_maskb_clear = BFIN_UART_GCTL,
+ AWA_maskb_set = BFIN_UART_GCTL,
+ AWA_maskb_toggle = BFIN_UART_GCTL,
AWA_dir = SPORT1_STAT,
AWA_polar = SPORT1_STAT,
AWA_edge = SPORT1_STAT,
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 1ded945a6fa..d9ba2b11e01 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -151,26 +151,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
- p0.h = hi(UART_LCR);
- p0.l = lo(UART_LCR);
+ p0.h = hi(BFIN_UART_LCR);
+ p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
- p0.h = hi(UART_DLL);
- p0.l = lo(UART_DLL);
+ p0.h = hi(BFIN_UART_DLL);
+ p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_DLH);
- p0.l = lo(UART_DLH);
+ p0.h = hi(BFIN_UART_DLH);
+ p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_GCTL);
- p0.l = lo(UART_GCTL);
+ p0.h = hi(BFIN_UART_GCTL);
+ p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index ac85fdfbfd0..9e9fac9c634 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -182,26 +182,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
- p0.h = hi(UART_LCR);
- p0.l = lo(UART_LCR);
+ p0.h = hi(BFIN_UART_LCR);
+ p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
- p0.h = hi(UART_DLL);
- p0.l = lo(UART_DLL);
+ p0.h = hi(BFIN_UART_DLL);
+ p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_DLH);
- p0.l = lo(UART_DLH);
+ p0.h = hi(BFIN_UART_DLH);
+ p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_GCTL);
- p0.l = lo(UART_GCTL);
+ p0.h = hi(BFIN_UART_GCTL);
+ p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 96a3d456fb6..279e2e812a2 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -139,26 +139,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
- p0.h = hi(UART_LCR);
- p0.l = lo(UART_LCR);
+ p0.h = hi(BFIN_UART_LCR);
+ p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
- p0.h = hi(UART_DLL);
- p0.l = lo(UART_DLL);
+ p0.h = hi(BFIN_UART_DLL);
+ p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_DLH);
- p0.l = lo(UART_DLH);
+ p0.h = hi(BFIN_UART_DLH);
+ p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_GCTL);
- p0.l = lo(UART_GCTL);
+ p0.h = hi(BFIN_UART_GCTL);
+ p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;