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authorTony Luck <tony.luck@intel.com>2008-10-17 13:47:53 -0700
committerTony Luck <tony.luck@intel.com>2008-10-17 13:47:53 -0700
commita9894a4a3c7fb53258d46dafe9dd4f45369fd9dd (patch)
tree9c82955ea3039980ad3432ccb1801cdb66e112c5 /arch
parent26e9a397774a0e94efbb8a0bf4a952c28d808cab (diff)
[IA64] Fix annoying IA64_TR_ALLOC_MAX message.
Madison cpus support 64 TR registers. Increase IA64_TR_ALLOC_MAX to 64. Also fixup the messages that get printed when this limit is exceeded. Repeating for every cpu is too noisy. Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/ia64/include/asm/kregs.h2
-rw-r--r--arch/ia64/mm/tlb.c8
2 files changed, 7 insertions, 3 deletions
diff --git a/arch/ia64/include/asm/kregs.h b/arch/ia64/include/asm/kregs.h
index aefcdfee7f2..39e65f6639f 100644
--- a/arch/ia64/include/asm/kregs.h
+++ b/arch/ia64/include/asm/kregs.h
@@ -32,7 +32,7 @@
#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
#define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/
-#define IA64_TR_ALLOC_MAX 32 /* Max number for dynamic use*/
+#define IA64_TR_ALLOC_MAX 64 /* Max number for dynamic use*/
/* Processor status register bits: */
#define IA64_PSR_BE_BIT 1
diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c
index 8caf42471f0..bd9818a36b4 100644
--- a/arch/ia64/mm/tlb.c
+++ b/arch/ia64/mm/tlb.c
@@ -362,9 +362,13 @@ ia64_tlb_init (void)
per_cpu(ia64_tr_num, cpu) =
vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
+ static int justonce = 1;
per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
- printk(KERN_DEBUG "TR register number exceeds IA64_TR_ALLOC_MAX!"
- "IA64_TR_ALLOC_MAX should be extended\n");
+ if (justonce) {
+ justonce = 0;
+ printk(KERN_DEBUG "TR register number exceeds "
+ "IA64_TR_ALLOC_MAX!\n");
+ }
}
}