MERGE-andy-tracking-patchset-edits

5 files changed, 1 insertions, 273 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2dfd1c28ae7..27d4dffc327 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1086,8 +1086,7 @@ endmenu
 
 menu "CPU Power Management"
 
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || \
-    ARCH_S3C64XX)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
 
 source "drivers/cpufreq/Kconfig"
 
@@ -1127,10 +1126,6 @@ config CPU_FREQ_PXA
 	default y
 	select CPU_FREQ_DEFAULT_GOV_USERSPACE
 
-config CPU_FREQ_S3C64XX
-	bool "CPUfreq support for S3C64xx CPUs"
-	depends on CPU_FREQ && CPU_S3C6410
-
 endif
 
 source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/plat-s3c/include/mach/cpu.h b/arch/arm/plat-s3c/include/mach/cpu.h
deleted file mode 100644
index 81571a2da7a..00000000000
--- a/arch/arm/plat-s3c/include/mach/cpu.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * arch/arm/plat-s3c/include/mach/cpu.h
- *
- *  S3C cpu type detection
- *
- *  Copyright (C) 2008 Samsung Electronics
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from OMAP cpu.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_S3C_CPU_H
-#define __ASM_ARCH_S3C_CPU_H
-
-extern unsigned int system_rev;
-
-/*
- * cpu_is_s3c24xx():	True for s3c2400, s3c2410, s3c2440 and so on
- * cpu_is_s3c241x():	True fro s3c2410, s3c2412
- * cpu_is_s3c244x():	True fro s3c2440, s3c2442, s3c2443
- * cpu_is_s3c64xx():	True for s3c6400, s3c6410
- */
-#define GET_S3C_CLASS	((system_rev >> 24) & 0xff)
-
-#define IS_S3C_CLASS(class, id)						\
-static inline int is_s3c ##class (void)					\
-{									\
-	return (GET_S3C_CLASS == (id)) ? 1 : 0;				\
-}
-
-#define GET_S3C_SUBCLASS	((system_rev >> 20) & 0xfff)
-
-#define IS_S3C_SUBCLASS(subclass, id)					\
-static inline int is_s3c ##subclass (void)				\
-{									\
-	return (GET_S3C_SUBCLASS == (id)) ? 1 : 0;			\
-}
-
-IS_S3C_CLASS(24xx, 0x24)
-IS_S3C_CLASS(64xx, 0x64)
-
-IS_S3C_SUBCLASS(241x, 0x241)
-IS_S3C_SUBCLASS(244x, 0x244)
-
-#define cpu_is_s3c24xx()		0
-#define cpu_is_s3c241x()		0
-#define cpu_is_s3c244x()		0
-#define cpu_is_s3c64xx()		0
-
-#if defined(CONFIG_ARCH_S3C2410)
-# undef  cpu_is_s3c24xx
-# undef  cpu_is_s3c241x
-# undef  cpu_is_s3c244x
-# define cpu_is_s3c24xx()		is_s3c24xx()
-# define cpu_is_s3c241x()		is_s3c241x()
-# define cpu_is_s3c244x()		is_s3c244x()
-#endif
-
-#if defined(CONFIG_ARCH_S3C64XX)
-# undef  cpu_is_s3c64xx
-# define cpu_is_s3c64xx()		is_s3c64xx()
-#endif
-
-/*
- * Macros to detect individual cpu types.
- * cpu_is_s3c2410():	True for s3c2410
- * cpu_is_s3c2440():	True for s3c2440
- * cpu_is_s3c6400():	True for s3c6400
- * cpu_is_s3c6410():	True for s3c6410
- *
- * Exception:
- * Store Revision A to 1
- * s3c2410a -> s3c2411
- * s3c2440a -> s3c2441
- */
-
-#define GET_S3C_TYPE	((system_rev >> 16) & 0xffff)
-
-#define IS_S3C_TYPE(type, id)						\
-static inline int is_s3c ##type (void)					\
-{									\
-	return (GET_S3C_TYPE == (id)) ? 1 : 0;				\
-}
-
-IS_S3C_TYPE(2400, 0x2400)
-IS_S3C_TYPE(2410, 0x2410)
-IS_S3C_TYPE(2410a, 0x2411)
-IS_S3C_TYPE(2412, 0x2412)
-IS_S3C_TYPE(2440, 0x2440)
-IS_S3C_TYPE(2440a, 0x2441)
-IS_S3C_TYPE(2442, 0x2442)
-IS_S3C_TYPE(2443, 0x2443)
-IS_S3C_TYPE(6400, 0x6400)
-IS_S3C_TYPE(6410, 0x6410)
-
-#define cpu_is_s3c2400()		0
-#define cpu_is_s3c2410()		0
-#define cpu_is_s3c2410a()		0
-#define cpu_is_s3c2412()		0
-#define cpu_is_s3c2440()		0
-#define cpu_is_s3c2440a()		0
-#define cpu_is_s3c2442()		0
-#define cpu_is_s3c2443()		0
-#define cpu_is_s3c6400()		0
-#define cpu_is_s3c6410()		0
-
-#if defined(CONFIG_ARCH_S3C2410)
-# undef  cpu_is_s3c2400
-# define cpu_is_s3c2400()		is_s3c2400()
-#endif
-
-#if defined(CONFIG_CPU_S3C2410)
-# undef  cpu_is_s3c2410
-# undef  cpu_is_s3c2410a
-# define cpu_is_s3c2410()		is_s3c2410()
-# define cpu_is_s3c2410a()		is_s3c2410a()
-#endif
-
-#if defined(CONFIG_CPU_S3C2412)
-# undef  cpu_is_s3c2412
-# define cpu_is_s3c2412()		is_s3c2412()
-#endif
-
-#if defined(CONFIG_CPU_S3C2440)
-# undef  cpu_is_s3c2440
-# undef  cpu_is_s3c2440a
-# define cpu_is_s3c2440()		is_s3c2440()
-# define cpu_is_s3c2440a()		is_s3c2440a()
-#endif
-
-#if defined(CONFIG_CPU_S3C2442)
-# undef  cpu_is_s3c2442
-# define cpu_is_s3c2442()		is_s3c2442()
-#endif
-
-#if defined(CONFIG_CPU_S3C2443)
-# undef  cpu_is_s3c2443
-# define cpu_is_s3c2443()		is_s3c2443()
-#endif
-
-#if defined(CONFIG_ARCH_S3C64XX)
-# undef  cpu_is_s3c6400
-# undef  cpu_is_s3c6410
-# define cpu_is_s3c6400()		is_s3c6400()
-# define cpu_is_s3c6410()		is_s3c6410()
-#endif
-
-#endif
diff --git a/arch/arm/plat-s3c/init.c b/arch/arm/plat-s3c/init.c
index f63ff9c86c3..6790edfaca6 100644
--- a/arch/arm/plat-s3c/init.c
+++ b/arch/arm/plat-s3c/init.c
@@ -31,31 +31,6 @@
 
 static struct cpu_table *cpu;
 
-static void __init set_system_rev(unsigned int idcode)
-{
-	/*
-	 * system_rev encoding is as follows
-	 * system_rev & 0xff000000 -> S3C Class (24xx/64xx)
-	 * system_rev & 0xfff00000 -> S3C Sub Class (241x/244x)
-	 * system_rev & 0xffff0000 -> S3C Type (2410/2440/6400/6410)
-	 *
-	 * Remains[15:0] are reserved
-	 *
-	 * Exception:
-	 *  Store Revision A to 1 such as
-	 *  s3c2410A to s3c2411
-	 *  s3c2440A to s3c2441
-	 */
-	system_rev = (idcode & 0x0ffff000) << 4;
-
-	if (idcode == 0x32410002 || idcode == 0x32440001)
-		system_rev |= (0x1 << 16);
-	if (idcode == 0x32440aaa)	/* s3c2442 */
-		system_rev |= (0x2 << 16);
-	if (idcode == 0x0)		/* s3c2400 */
-		system_rev |= (0x2400 << 16);
-}
-
 static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
 						struct cpu_table *tab,
 						unsigned int count)
@@ -78,8 +53,6 @@ void __init s3c_init_cpu(unsigned long idcode,
 		panic("Unknown S3C24XX CPU");
 	}
 
-	set_system_rev(idcode);
-
 	printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
 
 	if (cpu->map_io == NULL || cpu->init == NULL) {
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 0d5a9cdf3bb..4ecefb68252 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -34,8 +34,6 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)		+= sleep.o
 obj-$(CONFIG_PM)		+= irq-pm.o
 
-obj-$(CONFIG_CPU_FREQ_S3C64XX)	+= cpufreq.o
-
 # Device setup
 
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 2dc67331c89..a6f6b91b732 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -24,7 +24,6 @@
 
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <mach/cpu.h>
 
 #include <plat/cpu-freq.h>
 
@@ -89,80 +88,6 @@ struct clksrc_clk clk_mout_apll = {
 	.sources	= &clk_src_apll,
 };
 
-static u32 clk_arm_div_mask(void)
-{
-	if (cpu_is_s3c6400())
-		return S3C6400_CLKDIV0_ARM_MASK;
-
-	if (cpu_is_s3c6410())
-		return S3C6410_CLKDIV0_ARM_MASK;
-
-	return 0;
-}
-
-static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
-{
-	unsigned long rate = clk_get_rate(clk->parent);
-	u32 val;
-
-	val = __raw_readl(S3C_CLK_DIV0);
-	val &= clk_arm_div_mask();
-
-	return rate / (val + 1);
-}
-
-static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
-						unsigned long rate)
-{
-	unsigned long parent = clk_get_rate(clk->parent);
-	int div;
-	int max = clk_arm_div_mask() + 1;
-
-	if (parent < rate)
-		return parent;
-
-	div = parent / rate;
-
-	if (div < 1)
-		div = 1;
-	if (div > max)
-		div = max;
-
-	return parent / div;
-}
-
-static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned int div;
-	u32 val;
-	unsigned long flags;
-
-	rate = clk_round_rate(clk, rate);
-	div = (clk_get_rate(clk->parent) / rate) - 1;
-
-	if (div > clk_arm_div_mask())
-		return -EINVAL;
-
-	val = __raw_readl(S3C_CLK_DIV0);
-	val &= ~clk_arm_div_mask();
-	val |= div;
-
-	local_irq_save(flags);
-	__raw_writel(val, S3C_CLK_DIV0);
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-static struct clk clk_arm = {
-	.name		= "armclk",
-	.id		= -1,
-	.parent		= &clk_mout_apll.clk,
-	.round_rate	= &s3c64xx_clk_arm_round_rate,
-	.get_rate	= s3c64xx_clk_arm_get_rate,
-	.set_rate	= s3c64xx_clk_arm_set_rate,
-};
-
 struct clk clk_fout_epll = {
 	.name		= "fout_epll",
 	.id		= -1,
@@ -708,7 +633,6 @@ static struct clk *clks[] __initdata = {
 	&clk_audio0.clk,
 	&clk_audio1.clk,
 	&clk_irda.clk,
-	&clk_arm,
 };
 
 void __init s3c6400_register_clocks(void)