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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-08-10 20:58:46 +0400
committerJeff Garzik <jeff@garzik.org>2007-08-15 04:19:07 -0400
commitd44a65f7bb0dae0bcc78de336b55a75b30ec2d2a (patch)
tree22c2eb369022138b5da775c791e5126c7068d8b0 /drivers/ata/pata_hpt3x2n.c
parentbe456b77ffbd3983b5da8eff49a70a701333f68b (diff)
pata_hpt37x: actually clock HPT374 with 50 MHz DPLL (take 2)
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask including mode 5 used to check for the necessity of 66 MHz clocking -- this caused 66 MHz clock to be used for HPT374 chip that does not tolerate it. While fixing this, also remove PLL mode from the TODO list -- I don't think it's still a relevant item. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_hpt3x2n.c')
0 files changed, 0 insertions, 0 deletions