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authorOlaf Hering <olaf@aepfle.de>2007-02-10 21:36:14 +0100
committerJeff Garzik <jeff@garzik.org>2007-02-15 18:04:53 -0500
commit8361cd79f2434d43054be894baf08a74dae5f8c0 (patch)
tree952230cb835c3a390f7b0c2ec7b36040cea21d5a /drivers/ata
parent9f271d576a79f74a543c4099a014d8d4eafa737d (diff)
add delay around sl82c105_reset_engine calls
The hald media changed polling does really confuse things. Noone knows why the delays are needed, but they give us access to the CD. An udelay(50) will give reliable access to the drive, but there is still one (or more) EH reset. The drive works without EH resets with udelay(100). Signed-off-by: Olaf Hering <olaf@aepfle.de> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/pata_sl82c105.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index f2fa158d07c..96e890fd645 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -187,7 +187,9 @@ static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
+ udelay(100);
sl82c105_reset_engine(ap);
+ udelay(100);
/* Set the clocks for DMA */
sl82c105_configure_dmamode(ap, qc->dev);
@@ -216,6 +218,7 @@ static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
ata_bmdma_stop(qc);
sl82c105_reset_engine(ap);
+ udelay(100);
/* This will redo the initial setup of the DMA device to matching
PIO timings */