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authorArthur Jones <ajones@riverbed.com>2008-07-25 01:49:06 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2008-07-25 10:53:48 -0700
commit43920a598f9358a12eb59eeddc4cd950f03aea8c (patch)
tree8008a71e74ad49df95f7d74a99f994a416f71a64 /drivers/edac
parentf7952ffcffa88c9a3fa92c26081f4ec9143c680f (diff)
edac: i5100 fix enable ecc hardware
It is possible that the BIOS did not enable ECC at boot time. We check for that case and fail to load if it is true. Signed-off-by: Arthur Jones <ajones@riverbed.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/i5100_edac.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index a8767a6c148..509eec860c3 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -24,6 +24,8 @@
/* register addresses and bit field accessors... */
/* device 16, func 1 */
+#define I5100_MC 0x40 /* Memory Control Register */
+#define I5100_MC_ERRDETEN(a) ((a) >> 5 & 1)
#define I5100_MS 0x44 /* Memory Status Register */
#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
#define I5100_SPDDATA_RDO(a) ((a) >> 15 & 1)
@@ -688,6 +690,14 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
goto bail;
}
+ /* ECC enabled? */
+ pci_read_config_dword(pdev, I5100_MC, &dw);
+ if (!I5100_MC_ERRDETEN(dw)) {
+ printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
+ ret = -ENODEV;
+ goto bail;
+ }
+
/* figure out how many ranks, from strapped state of 48GB_Mode input */
pci_read_config_dword(pdev, I5100_MS, &dw);
ranksperch = !!(dw & (1 << 8)) * 2 + 4;