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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-01 09:19:42 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-01 09:19:42 -0700 |
| commit | 42be79e37e264557f12860fa4cc84b4de3685954 (patch) | |
| tree | 8ead77e9bb5ed55412c71e2f6fd8e6b8d4581da6 /drivers/gpu/drm/nouveau/nv50_graph.c | |
| parent | 445c682b93479c06d1b062b63ed79202f3ed5503 (diff) | |
| parent | d668046c13024d74af7d04a124ba55f406380fe7 (diff) | |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (76 commits)
drm/radeon/kms: enable ACPI powermanagement mode on radeon gpus.
drm/radeon/kms: rs400/480 should set common registers.
drm/radeon/kms: add sanity check to wptr.
drm/radeon/kms/evergreen: get DP working
drm/radeon/kms: add hw_i2c module option
drm/radeon/kms: use new pre/post_xfer i2c bit algo hooks
drm/radeon/kms: disable MSI on IGP chips
drm/radeon/kms: display watermark updates (v2)
drm/radeon/kms/dp: disable training pattern on the sink at the end of link training
drm/radeon/kms: minor fixes for eDP with LCD* device tags (v2)
drm/radeon/kms/dp: remove extraneous training complete call
drm/radeon/kms/atom: minor fixes to transmitter setup
drm/radeon/kms: Only restrict BO to visible VRAM size when pinning to VRAM.
drm: fix build error when SYSRQ is disabled
drm/radeon/kms: fix macbookpro connector quirk
drm/radeon/r6xx/r7xx: further safe reg clean up
drm/radeon: bump the UMS driver version for r6xx/r7xx const buffer support
drm/radeon/kms: bump the version for r6xx/r7xx const buffer support
drm/radeon/r6xx/r7xx: CS parser fixes
drm/radeon/kms: fix some typos in r6xx/r7xx hpd setup
...
Fix up MSI-related conflicts in drivers/gpu/drm/radeon/radeon_irq_kms.c
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_graph.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_graph.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index 857a09671a3..c62b33a02f8 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c @@ -56,6 +56,10 @@ nv50_graph_init_intr(struct drm_device *dev) static void nv50_graph_init_regs__nv(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t units = nv_rd32(dev, 0x1540); + int i; + NV_DEBUG(dev, "\n"); nv_wr32(dev, 0x400804, 0xc0000000); @@ -65,6 +69,20 @@ nv50_graph_init_regs__nv(struct drm_device *dev) nv_wr32(dev, 0x405018, 0xc0000000); nv_wr32(dev, 0x402000, 0xc0000000); + for (i = 0; i < 16; i++) { + if (units & 1 << i) { + if (dev_priv->chipset < 0xa0) { + nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000); + nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000); + nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000); + } else { + nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000); + nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000); + nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000); + } + } + } + nv_wr32(dev, 0x400108, 0xffffffff); nv_wr32(dev, 0x400824, 0x00004000); @@ -229,10 +247,6 @@ nv50_graph_create_context(struct nouveau_channel *chan) nouveau_grctx_vals_load(dev, ctx); } nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12); - if ((dev_priv->chipset & 0xf0) == 0xa0) - nv_wo32(dev, ctx, 0x00004/4, 0x00000000); - else - nv_wo32(dev, ctx, 0x0011c/4, 0x00000000); dev_priv->engine.instmem.finish_access(dev); return 0; |