diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-09-05 18:56:57 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-09-05 18:56:57 +0200 |
commit | 616ad8c44281c0c6711a72b560e01ec335ff27e0 (patch) | |
tree | 0a20453ffedb09db6fb41a0c2208ccc2c7751d3a /drivers/gpu/drm/radeon/r300_reg.h | |
parent | 99809963c99e1ed868d9ebeb4a5e7ee1cbe0309f (diff) | |
parent | b380b0d4f7dffcc235c0facefa537d4655619101 (diff) |
Merge branch 'linus' into x86/defconfig
Diffstat (limited to 'drivers/gpu/drm/radeon/r300_reg.h')
-rw-r--r-- | drivers/gpu/drm/radeon/r300_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index a6802f26afc..ee6f811599a 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h @@ -317,7 +317,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and * avoids bugs caused by still running shaders reading bad data from memory. */ -#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 /* Absolutely no clue what this register is about. */ #define R300_VAP_UNKNOWN_2288 0x2288 @@ -513,7 +513,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* gap */ /* Zero to flush caches. */ -#define R300_TX_CNTL 0x4100 +#define R300_TX_INVALTAGS 0x4100 #define R300_TX_FLUSH 0x0 /* The upper enable bits are guessed, based on fglrx reported limits. */ @@ -1362,6 +1362,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ +#define R300_RB3D_AARESOLVE_CTL 0x4E88 /* gap */ /* Guess by Vladimir. |