aboutsummaryrefslogtreecommitdiff
path: root/drivers/mmc
diff options
context:
space:
mode:
authorBen Dooks <ben-linux@fluff.org>2008-11-03 20:18:59 +0000
committerBen Dooks <ben-linux@fluff.org>2008-11-03 20:30:50 +0000
commit5fc1f830353695d50a4ef5a20bbe6b19721eeaf8 (patch)
tree82057f8264af15bbefbf7f4782be06cc38daf0e1 /drivers/mmc
parent439c45acfde46ab914099a25bf0559567904f632 (diff)
SDHCI: Add quirk for controller with no end-of-busy IRQ
The Samsung SDHCI controller block seems to fail to generate an INT_DATA_END after the transfer has completed and the bus busy state finished. Changes in e809517f6fa5803a5a1cd56026f0e2190fc13d5c to use the new busy method are the cause of the behaviour change. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci.c15
-rw-r--r--drivers/mmc/host/sdhci.h3
2 files changed, 17 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 2827ccd9f35..f86f30058c1 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1291,11 +1291,24 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
* controllers.
*/
if (host->cmd->flags & MMC_RSP_BUSY) {
+ u32 present;
+
if (host->cmd->data)
DBG("Cannot wait for busy signal when also "
"doing a data transfer");
- else
+ else if (!(host->quirks & SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY))
return;
+
+ /* The Samsung SDHCI does not seem to provide an INT_DATA_END
+ * when the system goes non-busy, so check the state of the
+ * transfer by reading SDHCI_PRESENT_STATE to see if the
+ * controller is ready
+ */
+
+ present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
+ DBG("busy? present %08x, intstat %08x\n", present, intmask);
+
+ /* fall through and take the SDHCI_INT_RESPONSE */
}
if (intmask & SDHCI_INT_RESPONSE)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 9fbf0ddf241..209b78bb469 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -57,6 +57,7 @@
#define SDHCI_DATA_AVAILABLE 0x00000800
#define SDHCI_CARD_PRESENT 0x00010000
#define SDHCI_WRITE_PROTECT 0x00080000
+#define SDHCI_DATA_BIT(x) (1 << ((x) + 20))
#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_LED 0x01
@@ -210,6 +211,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
/* Controller supports high speed but doesn't have the caps bit set */
#define SDHCI_QUIRK_FORCE_HIGHSPEED (1<<14)
+/* Controller does not provide transfer-complete interrupt when not busy */
+#define SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY (1<<15)
int irq; /* Device IRQ */
void __iomem * ioaddr; /* Mapped address */