diff options
| author | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2008-04-02 13:48:13 -0700 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2008-04-16 20:41:36 -0400 |
| commit | e9ec2c0f4bfbe0632b22a2c0b74d5e1e96aeab66 (patch) | |
| tree | e65a632498dad6f7eaf77f1d2b00aa0c237d60a5 /drivers/net/e1000e/hw.h | |
| parent | 8d7c294cae6fd1474d88267810d1965f60a903af (diff) | |
e1000e: Make arrays out of these Rx/Tx registers
With multiple queues coming into the code these base control
registers need to be made into arrays.
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/e1000e/hw.h')
| -rw-r--r-- | drivers/net/e1000e/hw.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index 0b4145a7322..53f1ac6327f 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h @@ -93,6 +93,8 @@ enum e1e_registers { E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */ E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */ E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */ + E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */ +#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8)) E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */ /* Convenience macros @@ -111,11 +113,11 @@ enum e1e_registers { E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */ E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */ E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */ - E1000_TXDCTL = 0x03828, /* Tx Descriptor Control - RW */ + E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */ +#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8)) E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */ - E1000_TARC0 = 0x03840, /* Tx Arbitration Count (0) */ - E1000_TXDCTL1 = 0x03928, /* Tx Descriptor Control (1) - RW */ - E1000_TARC1 = 0x03940, /* Tx Arbitration Count (1) */ + E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */ +#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8)) E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ |