diff options
| author | Eugene Surovegin <ebs@ebshome.net> | 2005-10-29 12:45:31 -0700 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-10-29 18:06:54 -0400 |
| commit | 1b195916dd9111bbaf043d0dcfdc5d6908590c6e (patch) | |
| tree | 9b9b8dc2d68dfc1e80855d03e7596475b9291cac /drivers/net/ibm_emac/ibm_emac_core.c | |
| parent | 7ad8a89c2e8a930a902cb0622956b27796c027e5 (diff) | |
[PATCH] PPC 44x EMAC driver: add 440GR support
Add PowerPC 440GR support
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/ibm_emac/ibm_emac_core.c')
| -rw-r--r-- | drivers/net/ibm_emac/ibm_emac_core.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c index 48239e17d35..eb7d6947871 100644 --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c @@ -87,10 +87,11 @@ MODULE_LICENSE("GPL"); */ static u32 busy_phy_map; -#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP)) +#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \ + (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)) /* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us * with PHY RX clock problem. - * 440EP has more sane SDR0_MFR register implementation than 440GX, which + * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which * also allows controlling each EMAC clock */ static inline void EMAC_RX_CLK_TX(int idx) @@ -100,7 +101,7 @@ static inline void EMAC_RX_CLK_TX(int idx) #if defined(CONFIG_405EP) mtdcr(0xf3, mfdcr(0xf3) | (1 << idx)); -#else /* CONFIG_440EP */ +#else /* CONFIG_440EP || CONFIG_440GR */ SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx)); #endif |