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authorEilon Greenstein <eilong@broadcom.com>2008-11-03 16:46:19 -0800
committerDavid S. Miller <davem@davemloft.net>2008-11-03 16:46:19 -0800
commit7d96567ac0527703cf1b80043fc0ebd7f21a10ad (patch)
treec51fc21eb9149b8ac13bec127c8f9e6599a8164c /drivers/net
parent9a0354405feb0f8bd460349a93db05e4cca8d166 (diff)
bnx2x: PCI configuration bug on big-endian
The current code read nothing but zeros on big-endian (wrong part of the 32bits). This caused poor performance on big-endian machines. Though this issue did not cause the system to crash, the performance is significantly better with the fix so I view it as critical bug fix. Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2x_init.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 130927cfc75..a6c0b3abba2 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -564,14 +564,15 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
static void bnx2x_init_pxp(struct bnx2x *bp)
{
+ u16 devctl;
int r_order, w_order;
u32 val, i;
pci_read_config_word(bp->pdev,
- bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val);
- DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val);
- w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
- r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12);
+ bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
+ DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
+ w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+ r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
if (r_order > MAX_RD_ORD) {
DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",