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authorAuke Kok <auke-jan.h.kok@intel.com>2006-09-11 14:00:21 -0700
committerJeff Garzik <jeff@garzik.org>2006-09-12 11:46:39 -0400
commit6a9516989f94df10d9a27ba543c6b53b3e69c84a (patch)
treeb476d50e8b8126181847fb00326a871489457964 /drivers
parent1802ca745280b916cda4090e459741b8c9b3e8d0 (diff)
[PATCH] e1000: fix TX timout hang regression for 82542rev3
Commit 581d708eb47cccb5f41bc0817e50c9b004011ba8 (oct. 5 2005) introduced partial Multiqueue support for e1000 which broke macro smartness in setting up head/tail registers for 82542 rev3 chipsets, making these adapters completely non-working since 2.6.15. This commit sets the proper head and tail registers for read and write descriptor rings. Ths fix was tested on an 82542 rev3 NIC and newer NICs. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000/e1000_main.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 726f43d5593..98ef9f85482 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -1433,8 +1433,8 @@ e1000_configure_tx(struct e1000_adapter *adapter)
E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
E1000_WRITE_REG(hw, TDT, 0);
E1000_WRITE_REG(hw, TDH, 0);
- adapter->tx_ring[0].tdh = E1000_TDH;
- adapter->tx_ring[0].tdt = E1000_TDT;
+ adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
+ adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
break;
}
@@ -1840,8 +1840,8 @@ e1000_configure_rx(struct e1000_adapter *adapter)
E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
E1000_WRITE_REG(hw, RDT, 0);
E1000_WRITE_REG(hw, RDH, 0);
- adapter->rx_ring[0].rdh = E1000_RDH;
- adapter->rx_ring[0].rdt = E1000_RDT;
+ adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
+ adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
break;
}