diff options
| author | Ingo Molnar <mingo@elte.hu> | 2008-07-26 15:30:40 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-26 15:30:40 +0200 |
| commit | 1503af661947b7a4a09355cc2ae6aa0d43f16776 (patch) | |
| tree | 5bfcfadf2dd2d98c2ad251c96d7ee43a6903819a /include/asm-arm/arch-pxa/regs-ssp.h | |
| parent | a31863168660c6b6f6c7ffe05bb6a38e97803326 (diff) | |
| parent | 024e8ac04453b3525448c31ef39848cf675ba6db (diff) | |
Merge branch 'linus' into x86/header-guards
Conflicts:
include/asm-x86/gpio.h
include/asm-x86/ide.h
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-arm/arch-pxa/regs-ssp.h')
| -rw-r--r-- | include/asm-arm/arch-pxa/regs-ssp.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h index 0255328c3c1..3c04cde2cf1 100644 --- a/include/asm-arm/arch-pxa/regs-ssp.h +++ b/include/asm-arm/arch-pxa/regs-ssp.h @@ -20,6 +20,10 @@ #define SSTSS (0x38) /* SSP Timeslot Status */ #define SSACD (0x3C) /* SSP Audio Clock Divider */ +#if defined(CONFIG_PXA3xx) +#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ +#endif + /* Common PXA2xx bits first */ #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ @@ -29,10 +33,12 @@ #define SSCR0_National (0x2 << 4) /* National Microwire */ #define SSCR0_ECS (1 << 6) /* External clock select */ #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ + #if defined(CONFIG_PXA25x) #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ -#elif defined(CONFIG_PXA27x) + +#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ #define SSCR0_EDSS (1 << 20) /* Extended data size select */ @@ -45,6 +51,10 @@ #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ #endif +#if defined(CONFIG_PXA3xx) +#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ +#endif + #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ @@ -109,5 +119,9 @@ #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ +#if defined(CONFIG_PXA3xx) +#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ +#endif + #endif /* __ASM_ARCH_REGS_SSP_H */ |