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authorNicolas Pitre <nico@cam.org>2008-03-31 12:38:31 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 22:44:38 +0200
commit2239aff6ab2b95af1f628eee7a809f21c41605b3 (patch)
treefd940074a312d252976da05f7e4457c446e14027 /include/asm-arm
parent4c4925c1f4ccd72002957c3e73b4f117f2bcf712 (diff)
[ARM] cache align destination pointer when copying memory for some processors
The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/assembler.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce83282082..911393b2c6f 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
#endif
/*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory. Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+
+/*
* Enable and disable interrupts
*/
#if __LINUX_ARM_ARCH__ >= 6