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authorStanislav Samsonov <samsonov@marvell.com>2008-06-03 11:24:40 +0300
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 22:45:03 +0200
commit836a8051d54525e0782f156dcfa3c13d30f22840 (patch)
treea72c16e6bbfb4b4768562bc9757bdd04b17e4c7f /include/asm-arm
parent7ea217a85e38c5ed6edbc789670badb619da9f28 (diff)
[ARM] Feroceon: L1 cache range operation support
This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/cacheflush.h6
1 files changed, 1 insertions, 5 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56ee..b85d426bb52 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
#endif
#if defined(CONFIG_CPU_FEROCEON)
-# ifdef _CACHE
-# define MULTI_CACHE 1
-# else
-# define _CACHE feroceon
-# endif
+# define MULTI_CACHE 1
#endif
#if defined(CONFIG_CPU_V6)