diff options
| author | Russ Anderson <rja@sgi.com> | 2007-08-21 16:45:12 -0500 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-12-19 11:19:19 -0800 |
| commit | 64135fa97ce016058f95345425a9ebd04ee1bd2a (patch) | |
| tree | 7b7cd85c07a608db9e01b39694d9af7a823bdfdb /include/asm-ia64/sn/xp.h | |
| parent | 091062284c05d13b3393f4fcfcedc0f52cb948b4 (diff) | |
[IA64] Fix Altix BTE error return status
The Altix shub2 BTE error detail bits are in a different location
than on shub1. The current code does not take this into account
resulting in all shub2 BTE failures mapping to "unknown".
This patch reads the error detail bits from the proper location,
so the correct BTE failure reason is returned for both shub1
and shub2.
Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/sn/xp.h')
| -rw-r--r-- | include/asm-ia64/sn/xp.h | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h index 6f807e0193b..f7711b308e4 100644 --- a/include/asm-ia64/sn/xp.h +++ b/include/asm-ia64/sn/xp.h @@ -86,7 +86,7 @@ xp_bte_copy(u64 src, u64 vdst, u64 len, u64 mode, void *notification) BUG_ON(REGION_NUMBER(vdst) != RGN_KERNEL); ret = bte_copy(src, pdst, len, mode, notification); - if (ret != BTE_SUCCESS) { + if ((ret != BTE_SUCCESS) && BTE_ERROR_RETRY(ret)) { if (!in_interrupt()) { cond_resched(); } @@ -244,7 +244,30 @@ enum xpc_retval { xpcDisconnected, /* 51: channel disconnected (closed) */ - xpcUnknownReason /* 52: unknown reason -- must be last in list */ + xpcBteSh2Start, /* 52: BTE CRB timeout */ + + /* 53: 0x1 BTE Error Response Short */ + xpcBteSh2RspShort = xpcBteSh2Start + BTEFAIL_SH2_RESP_SHORT, + + /* 54: 0x2 BTE Error Response Long */ + xpcBteSh2RspLong = xpcBteSh2Start + BTEFAIL_SH2_RESP_LONG, + + /* 56: 0x4 BTE Error Response DSB */ + xpcBteSh2RspDSB = xpcBteSh2Start + BTEFAIL_SH2_RESP_DSP, + + /* 60: 0x8 BTE Error Response Access */ + xpcBteSh2RspAccess = xpcBteSh2Start + BTEFAIL_SH2_RESP_ACCESS, + + /* 68: 0x10 BTE Error CRB timeout */ + xpcBteSh2CRBTO = xpcBteSh2Start + BTEFAIL_SH2_CRB_TO, + + /* 84: 0x20 BTE Error NACK limit */ + xpcBteSh2NACKLimit = xpcBteSh2Start + BTEFAIL_SH2_NACK_LIMIT, + + /* 115: BTE end */ + xpcBteSh2End = xpcBteSh2Start + BTEFAIL_SH2_ALL, + + xpcUnknownReason /* 116: unknown reason -- must be last in list */ }; |