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authorIngo Molnar <mingo@elte.hu>2008-07-16 13:11:29 +0200
committerIngo Molnar <mingo@elte.hu>2008-07-16 13:11:29 +0200
commit77e442461c74068217b59b356cf18992c78ed896 (patch)
tree70f62a16bc6a81b63768279c9b40645d8f4dd4ff /include/asm-mips/mach-malta/war.h
parentd54191b85e294c46f05a2249b1f55ae54930bcc7 (diff)
parent45158894d4d6704afbb4cefe55e5f6ca279fe12a (diff)
Merge branch 'linus' into x86/kprobes
Diffstat (limited to 'include/asm-mips/mach-malta/war.h')
-rw-r--r--include/asm-mips/mach-malta/war.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-mips/mach-malta/war.h b/include/asm-mips/mach-malta/war.h
new file mode 100644
index 00000000000..7c6931d5f45
--- /dev/null
+++ b/include/asm-mips/mach-malta/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 1
+#define MIPS_CACHE_SYNC_WAR 1
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 1
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */