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authorRalf Baechle <ralf@linux-mips.org>2005-07-06 12:08:11 +0000
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 19:31:37 +0100
commit6e760c8dae7d6c47eff011dd4aad53c94d30494b (patch)
tree141699aef6e0a3b1fef03ec0c5cc8d8958851078 /include/asm-mips/pgtable-bits.h
parentca4973dd559b702e265688e724f356d289b8cd67 (diff)
Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/pgtable-bits.h')
-rw-r--r--include/asm-mips/pgtable-bits.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 3aad751ccd5..01e76e932e3 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
* unpredictable things. The code (when it is written) to deal with
* this problem will be in the update_mmu_cache() code for the r4k.
*/
-#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
#define _PAGE_PRESENT (1<<6) /* implemented in software */
#define _PAGE_READ (1<<7) /* implemented in software */
@@ -123,7 +123,7 @@
#endif
#endif
-#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
+#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -140,7 +140,7 @@
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
#endif
-#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
#else
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)