Merge Linux 2.6.23

author: David Woodhouse <dwmw2@infradead.org> 2007-10-13 14:43:54 +0100
committer: David Woodhouse <dwmw2@infradead.org> 2007-10-13 14:43:54 +0100
commit: b160292cc216a50fd0cd386b0bda2cd48352c73b (patch)
tree: ef07cf98f91353ee4c9ec1e1ca7a2a5d9d4b538a /include/asm-mips
parent: b37bde147890c8fea8369a5a4e230dabdea4ebfb (diff)
parent: bbf25010f1a6b761914430f5fca081ec8c7accd1 (diff)
30 files changed, 279 insertions, 1898 deletions
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
index 3646a3f2ed3..0ba9d6ef76a 100644
--- a/include/asm-mips/bcache.h
+++ b/include/asm-mips/bcache.h
@@ -21,7 +21,6 @@ struct bcache_ops {
 };
 
 extern void indy_sc_init(void);
-extern void sni_pcimt_sc_init(void);
 
 #ifdef CONFIG_BOARD_SCACHE
 
diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h
new file mode 100644
index 00000000000..c5b4708e003
--- /dev/null
+++ b/include/asm-mips/cmpxchg.h
@@ -0,0 +1,107 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_CMPXCHG_H
+#define __ASM_CMPXCHG_H
+
+#include <linux/irqflags.h>
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+#define __cmpxchg_asm(ld, st, m, old, new)				\
+({									\
+	__typeof(*(m)) __ret;						\
+									\
+	if (cpu_has_llsc && R10000_LLSC_WAR) {				\
+		__asm__ __volatile__(					\
+		"	.set	push				\n"	\
+		"	.set	noat				\n"	\
+		"	.set	mips3				\n"	\
+		"1:	" ld "	%0, %2		# __cmpxchg_asm	\n"	\
+		"	bne	%0, %z3, 2f			\n"	\
+		"	.set	mips0				\n"	\
+		"	move	$1, %z4				\n"	\
+		"	.set	mips3				\n"	\
+		"	" st "	$1, %1				\n"	\
+		"	beqzl	$1, 1b				\n"	\
+		"2:						\n"	\
+		"	.set	pop				\n"	\
+		: "=&r" (__ret), "=R" (*m)				\
+		: "R" (*m), "Jr" (old), "Jr" (new)			\
+		: "memory");						\
+	} else if (cpu_has_llsc) {					\
+		__asm__ __volatile__(					\
+		"	.set	push				\n"	\
+		"	.set	noat				\n"	\
+		"	.set	mips3				\n"	\
+		"1:	" ld "	%0, %2		# __cmpxchg_asm	\n"	\
+		"	bne	%0, %z3, 2f			\n"	\
+		"	.set	mips0				\n"	\
+		"	move	$1, %z4				\n"	\
+		"	.set	mips3				\n"	\
+		"	" st "	$1, %1				\n"	\
+		"	beqz	$1, 3f				\n"	\
+		"2:						\n"	\
+		"	.subsection 2				\n"	\
+		"3:	b	1b				\n"	\
+		"	.previous				\n"	\
+		"	.set	pop				\n"	\
+		: "=&r" (__ret), "=R" (*m)				\
+		: "R" (*m), "Jr" (old), "Jr" (new)			\
+		: "memory");						\
+	} else {							\
+		unsigned long __flags;					\
+									\
+		raw_local_irq_save(__flags);				\
+		__ret = *m;						\
+		if (__ret == old)					\
+			*m = new;					\
+		raw_local_irq_restore(__flags);				\
+	}								\
+									\
+	__ret;								\
+})
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __cmpxchg(ptr,old,new,barrier)					\
+({									\
+	__typeof__(ptr) __ptr = (ptr);					\
+	__typeof__(*(ptr)) __old = (old);				\
+	__typeof__(*(ptr)) __new = (new);				\
+	__typeof__(*(ptr)) __res = 0;					\
+									\
+	barrier;							\
+									\
+	switch (sizeof(*(__ptr))) {					\
+	case 4:								\
+		__res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new);	\
+		break;							\
+	case 8:								\
+		if (sizeof(long) == 8) {				\
+			__res = __cmpxchg_asm("lld", "scd", __ptr,	\
+					   __old, __new);		\
+			break;						\
+		}							\
+	default:							\
+		__cmpxchg_called_with_bad_pointer();			\
+		break;							\
+	}								\
+									\
+	barrier;							\
+									\
+	__res;								\
+})
+
+#define cmpxchg(ptr, old, new)		__cmpxchg(ptr, old, new, smp_llsc_mb())
+#define cmpxchg_local(ptr, old, new)	__cmpxchg(ptr, old, new,)
+
+#endif /* __ASM_CMPXCHG_H */
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
index 169ae26105e..aa6b876bbd7 100644
--- a/include/asm-mips/compiler.h
+++ b/include/asm-mips/compiler.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004  Maciej W. Rozycki
+ * Copyright (C) 2004, 2007  Maciej W. Rozycki
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -9,8 +9,10 @@
 #define _ASM_COMPILER_H
 
 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
+#define GCC_IMM_ASM "n"
 #define GCC_REG_ACCUM "$0"
 #else
+#define GCC_IMM_ASM "rn"
 #define GCC_REG_ACCUM "accum"
 #endif
 
diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h
index 83719eee2d1..4da0c1fe30d 100644
--- a/include/asm-mips/edac.h
+++ b/include/asm-mips/edac.h
@@ -9,8 +9,7 @@ static inline void atomic_scrub(void *va, u32 size)
 	unsigned long temp;
 	u32 i;
 
-	for (i = 0; i < size / sizeof(unsigned long); i++, virt_addr++) {
-
+	for (i = 0; i < size / sizeof(unsigned long); i++) {
 		/*
 		 * Very carefully read and write to memory atomically
 		 * so we are interrupt, DMA and SMP safe.
@@ -19,16 +18,16 @@ static inline void atomic_scrub(void *va, u32 size)
 		 */
 
 		__asm__ __volatile__ (
-		"       .set    mips3                                   \n"
-		"1:     ll      %0, %1          # atomic_add            \n"
-		"       ll      %0, %1          # atomic_add            \n"
-		"       addu    %0, $0                                  \n"
-		"       sc      %0, %1                                  \n"
-		"       beqz    %0, 1b                                  \n"
-		"       .set    mips0                                   \n"
+		"	.set	mips2					\n"
+		"1:	ll	%0, %1		# atomic_scrub		\n"
+		"	addu	%0, $0					\n"
+		"	sc	%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		"	.set	mips0					\n"
 		: "=&r" (temp), "=m" (*virt_addr)
 		: "m" (*virt_addr));
 
+		virt_addr++;
 	}
 }
 
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 00a50ec1c19..2a52333a062 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -13,6 +13,7 @@
 #define O_SYNC		0x0010
 #define O_NONBLOCK	0x0080
 #define O_CREAT         0x0100	/* not fcntl */
+#define O_TRUNC		0x0200	/* not fcntl */
 #define O_EXCL		0x0400	/* not fcntl */
 #define O_NOCTTY	0x0800	/* not fcntl */
 #define FASYNC		0x1000	/* fcntl, for BSD compatibility */
diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h
deleted file mode 100644
index 8f9bd341ed4..00000000000
--- a/include/asm-mips/gt64240.h
+++ /dev/null
@@ -1,1235 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright - Galileo technology.
- * Copyright (C) 2004 by Ralf Baechle
- */
-#ifndef __ASM_MIPS_MV64240_H
-#define __ASM_MIPS_MV64240_H
-
-#include <asm/addrspace.h>
-#include <asm/marvell.h>
-
-/*
- * CPU Control Registers
- */
-
-#define CPU_CONFIGURATION					0x000
-#define CPU_MODE						0x120
-#define CPU_READ_RESPONSE_CROSSBAR_LOW				0x170
-#define CPU_READ_RESPONSE_CROSSBAR_HIGH				0x178
-
-/*
- * Processor Address Space
- */
-
-/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS				0x008
-#define SCS_0_HIGH_DECODE_ADDRESS				0x010
-#define SCS_1_LOW_DECODE_ADDRESS				0x208
-#define SCS_1_HIGH_DECODE_ADDRESS				0x210
-#define SCS_2_LOW_DECODE_ADDRESS				0x018
-#define SCS_2_HIGH_DECODE_ADDRESS				0x020
-#define SCS_3_LOW_DECODE_ADDRESS				0x218
-#define SCS_3_HIGH_DECODE_ADDRESS				0x220
-/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS					0x028
-#define CS_0_HIGH_DECODE_ADDRESS				0x030
-#define CS_1_LOW_DECODE_ADDRESS					0x228
-#define CS_1_HIGH_DECODE_ADDRESS				0x230
-#define CS_2_LOW_DECODE_ADDRESS					0x248
-#define CS_2_HIGH_DECODE_ADDRESS				0x250
-#define CS_3_LOW_DECODE_ADDRESS					0x038
-#define CS_3_HIGH_DECODE_ADDRESS				0x040
-#define BOOTCS_LOW_DECODE_ADDRESS				0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS				0x240
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS				0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS				0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS				0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS			0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS				0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS			0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS				0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS			0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS				0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS			0x288
-
-#define PCI_1I_O_LOW_DECODE_ADDRESS				0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS				0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS				0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS			0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS				0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS			0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS				0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS			0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS				0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS			0x2b8
-
-#define INTERNAL_SPACE_DECODE					0x068
-
-#define CPU_0_LOW_DECODE_ADDRESS				0x290
-#define CPU_0_HIGH_DECODE_ADDRESS				0x298
-#define CPU_1_LOW_DECODE_ADDRESS				0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS				0x2c8
-
-#define PCI_0I_O_ADDRESS_REMAP					0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP				0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP				0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP				0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP				0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP				0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP				0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP				0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP				0x338
-
-#define PCI_1I_O_ADDRESS_REMAP					0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP				0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP				0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP				0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP				0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP				0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP				0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP				0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP				0x358
-
-/*
- * CPU Sync Barrier
- */
-
-#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER			0x0c0
-#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER			0x0c8
-
-
-/*
- * CPU Access Protect
- */
-
-#define CPU_LOW_PROTECT_ADDRESS_0				0X180
-#define CPU_HIGH_PROTECT_ADDRESS_0				0X188
-#define CPU_LOW_PROTECT_ADDRESS_1				0X190
-#define CPU_HIGH_PROTECT_ADDRESS_1				0X198
-#define CPU_LOW_PROTECT_ADDRESS_2				0X1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2				0X1a8
-#define CPU_LOW_PROTECT_ADDRESS_3				0X1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3				0X1b8
-#define CPU_LOW_PROTECT_ADDRESS_4				0X1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4				0X1c8
-#define CPU_LOW_PROTECT_ADDRESS_5				0X1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5				0X1d8
-#define CPU_LOW_PROTECT_ADDRESS_6				0X1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6				0X1e8
-#define CPU_LOW_PROTECT_ADDRESS_7				0X1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7				0X1f8
-
-
-/*
- * Snoop Control
- */
-
-#define SNOOP_BASE_ADDRESS_0					0x380
-#define SNOOP_TOP_ADDRESS_0					0x388
-#define SNOOP_BASE_ADDRESS_1					0x390
-#define SNOOP_TOP_ADDRESS_1					0x398
-#define SNOOP_BASE_ADDRESS_2					0x3a0
-#define SNOOP_TOP_ADDRESS_2					0x3a8
-#define SNOOP_BASE_ADDRESS_3					0x3b0
-#define SNOOP_TOP_ADDRESS_3					0x3b8
-
-/*
- * CPU Error Report
- */
-
-#define CPU_ERROR_ADDRESS_LOW					0x070
-#define CPU_ERROR_ADDRESS_HIGH					0x078
-#define CPU_ERROR_DATA_LOW					0x128
-#define CPU_ERROR_DATA_HIGH					0x130
-#define CPU_ERROR_PARITY					0x138
-#define CPU_ERROR_CAUSE						0x140
-#define CPU_ERROR_MASK						0x148
-
-/*
- * Pslave Debug
- */
-
-#define X_0_ADDRESS						0x360
-#define X_0_COMMAND_ID						0x368
-#define X_1_ADDRESS						0x370
-#define X_1_COMMAND_ID						0x378
-#define WRITE_DATA_LOW						0x3c0
-#define WRITE_DATA_HIGH						0x3c8
-#define WRITE_BYTE_ENABLE					0X3e0
-#define READ_DATA_LOW						0x3d0
-#define READ_DATA_HIGH						0x3d8
-#define READ_ID							0x3e8
-
-
-/*
- * SDRAM and Device Address Space
- */
-
-
-/*
- * SDRAM Configuration
- */
-
-#define SDRAM_CONFIGURATION					0x448
-#define SDRAM_OPERATION_MODE					0x474
-#define SDRAM_ADDRESS_DECODE					0x47C
-#define SDRAM_TIMING_PARAMETERS					0x4b4
-#define SDRAM_UMA_CONTROL					0x4a4
-#define SDRAM_CROSS_BAR_CONTROL_LOW				0x4a8
-#define SDRAM_CROSS_BAR_CONTROL_HIGH				0x4ac
-#define SDRAM_CROSS_BAR_TIMEOUT					0x4b0
-
-
-/*
- * SDRAM Parameters
- */
-
-#define SDRAM_BANK0PARAMETERS					0x44C
-#define SDRAM_BANK1PARAMETERS					0x450
-#define SDRAM_BANK2PARAMETERS					0x454
-#define SDRAM_BANK3PARAMETERS					0x458
-
-
-/*
- * SDRAM Error Report
- */
-
-#define SDRAM_ERROR_DATA_LOW					0x484
-#define SDRAM_ERROR_DATA_HIGH					0x480
-#define SDRAM_AND_DEVICE_ERROR_ADDRESS				0x490
-#define SDRAM_RECEIVED_ECC					0x488
-#define SDRAM_CALCULATED_ECC					0x48c
-#define SDRAM_ECC_CONTROL					0x494
-#define SDRAM_ECC_ERROR_COUNTER					0x498
-
-
-/*
- * SDunit Debug (for internal use)
- */
-
-#define X0_ADDRESS						0x500
-#define X0_COMMAND_AND_ID					0x504
-#define X0_WRITE_DATA_LOW					0x508
-#define X0_WRITE_DATA_HIGH					0x50c
-#define X0_WRITE_BYTE_ENABLE					0x518
-#define X0_READ_DATA_LOW					0x510
-#define X0_READ_DATA_HIGH					0x514
-#define X0_READ_ID						0x51c
-#define X1_ADDRESS						0x520
-#define X1_COMMAND_AND_ID					0x524
-#define X1_WRITE_DATA_LOW					0x528
-#define X1_WRITE_DATA_HIGH					0x52c
-#define X1_WRITE_BYTE_ENABLE					0x538
-#define X1_READ_DATA_LOW					0x530
-#define X1_READ_DATA_HIGH					0x534
-#define X1_READ_ID						0x53c
-#define X0_SNOOP_ADDRESS					0x540
-#define X0_SNOOP_COMMAND					0x544
-#define X1_SNOOP_ADDRESS					0x548
-#define X1_SNOOP_COMMAND					0x54c
-
-
-/*
- * Device Parameters
- */
-
-#define DEVICE_BANK0PARAMETERS					0x45c
-#define DEVICE_BANK1PARAMETERS					0x460
-#define DEVICE_BANK2PARAMETERS					0x464
-#define DEVICE_BANK3PARAMETERS					0x468
-#define DEVICE_BOOT_BANK_PARAMETERS				0x46c
-#define DEVICE_CONTROL						0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW				0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH				0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT				0x4c4
-
-
-/*
- * Device Interrupt
- */
-
-#define DEVICE_INTERRUPT_CAUSE					0x4d0
-#define DEVICE_INTERRUPT_MASK					0x4d4
-#define DEVICE_ERROR_ADDRESS					0x4d8
-
-/*
- * DMA Record
- */
-
-#define CHANNEL0_DMA_BYTE_COUNT					0x800
-#define CHANNEL1_DMA_BYTE_COUNT					0x804
-#define CHANNEL2_DMA_BYTE_COUNT					0x808
-#define CHANNEL3_DMA_BYTE_COUNT					0x80C
-#define CHANNEL4_DMA_BYTE_COUNT					0x900
-#define CHANNEL5_DMA_BYTE_COUNT					0x904
-#define CHANNEL6_DMA_BYTE_COUNT					0x908
-#define CHANNEL7_DMA_BYTE_COUNT					0x90C
-#define CHANNEL0_DMA_SOURCE_ADDRESS				0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS				0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS				0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS				0x81C
-#define CHANNEL4_DMA_SOURCE_ADDRESS				0x910
-#define CHANNEL5_DMA_SOURCE_ADDRESS				0x914
-#define CHANNEL6_DMA_SOURCE_ADDRESS				0x918
-#define CHANNEL7_DMA_SOURCE_ADDRESS				0x91C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS			0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS			0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS			0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS			0x82C
-#define CHANNEL4_DMA_DESTINATION_ADDRESS			0x920
-#define CHANNEL5_DMA_DESTINATION_ADDRESS			0x924
-#define CHANNEL6_DMA_DESTINATION_ADDRESS			0x928
-#define CHANNEL7_DMA_DESTINATION_ADDRESS			0x92C
-#define CHANNEL0NEXT_RECORD_POINTER				0x830
-#define CHANNEL1NEXT_RECORD_POINTER				0x834
-#define CHANNEL2NEXT_RECORD_POINTER				0x838
-#define CHANNEL3NEXT_RECORD_POINTER				0x83C
-#define CHANNEL4NEXT_RECORD_POINTER				0x930
-#define CHANNEL5NEXT_RECORD_POINTER				0x934
-#define CHANNEL6NEXT_RECORD_POINTER				0x938
-#define CHANNEL7NEXT_RECORD_POINTER				0x93C
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER			0x870
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER			0x874
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER			0x878
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER			0x87C
-#define CHANNEL4CURRENT_DESCRIPTOR_POINTER			0x970
-#define CHANNEL5CURRENT_DESCRIPTOR_POINTER			0x974
-#define CHANNEL6CURRENT_DESCRIPTOR_POINTER			0x978
-#define CHANNEL7CURRENT_DESCRIPTOR_POINTER			0x97C
-#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS			0x890
-#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS			0x894
-#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS			0x898
-#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS			0x89c
-#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS			0x990
-#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS			0x994
-#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS			0x998
-#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS			0x99c
-#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a0
-#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a4
-#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a8
-#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8ac
-#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a0
-#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a4
-#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a8
-#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9ac
-#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b0
-#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b4
-#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b8
-#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8bc
-#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b0
-#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b4
-#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b8
-#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9bc
-
-/*
- * DMA Channel Control
- */
-
-#define CHANNEL0CONTROL						0x840
-#define CHANNEL0CONTROL_HIGH					0x880
-
-#define CHANNEL1CONTROL						0x844
-#define CHANNEL1CONTROL_HIGH					0x884
-
-#define CHANNEL2CONTROL						0x848
-#define CHANNEL2CONTROL_HIGH					0x888
-
-#define CHANNEL3CONTROL						0x84C
-#define CHANNEL3CONTROL_HIGH					0x88C
-
-#define CHANNEL4CONTROL						0x940
-#define CHANNEL4CONTROL_HIGH					0x980
-
-#define CHANNEL5CONTROL						0x944
-#define CHANNEL5CONTROL_HIGH					0x984
-
-#define CHANNEL6CONTROL						0x948
-#define CHANNEL6CONTROL_HIGH					0x988
-
-#define CHANNEL7CONTROL						0x94C
-#define CHANNEL7CONTROL_HIGH					0x98C
-
-
-/*
- * DMA Arbiter
- */
-
-#define ARBITER_CONTROL_0_3					0x860
-#define ARBITER_CONTROL_4_7					0x960
-
-
-/*
- * DMA Interrupt
- */
-
-#define CHANELS0_3_INTERRUPT_CAUSE				0x8c0
-#define CHANELS0_3_INTERRUPT_MASK				0x8c4
-#define CHANELS0_3_ERROR_ADDRESS				0x8c8
-#define CHANELS0_3_ERROR_SELECT					0x8cc
-#define CHANELS4_7_INTERRUPT_CAUSE				0x9c0
-#define CHANELS4_7_INTERRUPT_MASK				0x9c4
-#define CHANELS4_7_ERROR_ADDRESS				0x9c8
-#define CHANELS4_7_ERROR_SELECT					0x9cc
-
-
-/*
- * DMA Debug (for internal use)
- */
-
-#define DMA_X0_ADDRESS						0x8e0
-#define DMA_X0_COMMAND_AND_ID					0x8e4
-#define DMA_X0_WRITE_DATA_LOW					0x8e8
-#define DMA_X0_WRITE_DATA_HIGH					0x8ec
-#define DMA_X0_WRITE_BYTE_ENABLE				0x8f8
-#define DMA_X0_READ_DATA_LOW					0x8f0
-#define DMA_X0_READ_DATA_HIGH					0x8f4
-#define DMA_X0_READ_ID						0x8fc
-#define DMA_X1_ADDRESS						0x9e0
-#define DMA_X1_COMMAND_AND_ID					0x9e4
-#define DMA_X1_WRITE_DATA_LOW					0x9e8
-#define DMA_X1_WRITE_DATA_HIGH					0x9ec
-#define DMA_X1_WRITE_BYTE_ENABLE				0x9f8
-#define DMA_X1_READ_DATA_LOW					0x9f0
-#define DMA_X1_READ_DATA_HIGH					0x9f4
-#define DMA_X1_READ_ID						0x9fc
-
-/*
- * Timer_Counter
- */
-
-#define TIMER_COUNTER0						0x850
-#define TIMER_COUNTER1						0x854
-#define TIMER_COUNTER2						0x858
-#define TIMER_COUNTER3						0x85C
-#define TIMER_COUNTER_0_3_CONTROL				0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE			0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK			0x86c
-#define TIMER_COUNTER4						0x950
-#define TIMER_COUNTER5						0x954
-#define TIMER_COUNTER6						0x958
-#define TIMER_COUNTER7						0x95C
-#define TIMER_COUNTER_4_7_CONTROL				0x964
-#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE			0x968
-#define TIMER_COUNTER_4_7_INTERRUPT_MASK			0x96c
-
-/*
- * PCI Slave Address Decoding
- */
-
-#define PCI_0SCS_0_BANK_SIZE					0xc08
-#define PCI_1SCS_0_BANK_SIZE					0xc88
-#define PCI_0SCS_1_BANK_SIZE					0xd08
-#define PCI_1SCS_1_BANK_SIZE					0xd88
-#define PCI_0SCS_2_BANK_SIZE					0xc0c
-#define PCI_1SCS_2_BANK_SIZE					0xc8c
-#define PCI_0SCS_3_BANK_SIZE					0xd0c
-#define PCI_1SCS_3_BANK_SIZE					0xd8c
-#define PCI_0CS_0_BANK_SIZE					0xc10
-#define PCI_1CS_0_BANK_SIZE					0xc90
-#define PCI_0CS_1_BANK_SIZE					0xd10
-#define PCI_1CS_1_BANK_SIZE					0xd90
-#define PCI_0CS_2_BANK_SIZE					0xd18
-#define PCI_1CS_2_BANK_SIZE					0xd98
-#define PCI_0CS_3_BANK_SIZE					0xc14
-#define PCI_1CS_3_BANK_SIZE					0xc94
-#define PCI_0CS_BOOT_BANK_SIZE					0xd14
-#define PCI_1CS_BOOT_BANK_SIZE					0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE					0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE					0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE					0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE					0xda0
-#define PCI_0P2P_I_O_BAR_SIZE					0xd24
-#define PCI_1P2P_I_O_BAR_SIZE					0xda4
-#define PCI_0CPU_BAR_SIZE					0xd28
-#define PCI_1CPU_BAR_SIZE					0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE				0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE				0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE				0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE				0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE				0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE				0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE				0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE				0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE					0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE					0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE					0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE					0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE					0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE					0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE					0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE					0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE				0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE				0xea0
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE				0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE				0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE				0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE				0xea8
-#define PCI_0DAC_CPU_BAR_SIZE					0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE					0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE				0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE				0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE			0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE			0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP				0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP				0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP				0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP				0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP				0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP				0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP				0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP				0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP				0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP				0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP				0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP				0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP				0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP				0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP				0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP				0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP			0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP			0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH			0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH			0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW			0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW			0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH			0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH			0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP				0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP				0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP				0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP				0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP			0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP			0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP			0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP			0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP			0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP			0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP			0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP			0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP			0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP			0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP			0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP			0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP			0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP			0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP			0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP			0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP			0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP			0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP				0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP				0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP			0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP			0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL				0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL				0xdbc
-
-/*
- * PCI Control
- */
-
-#define PCI_0COMMAND						0xc00
-#define PCI_1COMMAND						0xc80
-#define PCI_0MODE						0xd00
-#define PCI_1MODE						0xd80
-#define PCI_0TIMEOUT_RETRY					0xc04
-#define PCI_1TIMEOUT_RETRY					0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER				0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER				0xd84
-#define MSI_0TRIGGER_TIMER					0xc38
-#define MSI_1TRIGGER_TIMER					0xcb8
-#define PCI_0ARBITER_CONTROL					0x1d00
-#define PCI_1ARBITER_CONTROL					0x1d80
-/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW				 0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH				 0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT					 0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW		 0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH		 0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER			 0x1d10
-#define PCI_0P2P_CONFIGURATION					 0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW				 0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH				 0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0				 0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW				 0c1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH				 0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1				 0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW				 0c1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH				 0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2				 0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW				 0c1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH				 0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3				 0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW				 0c1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH				 0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4				 0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW				 0c1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH				 0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5				 0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW				 0c1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH				 0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6				 0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW				 0c1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH				 0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7				 0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW				 0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH				 0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT					 0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW		 0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH		 0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER			 0x1d90
-#define PCI_1P2P_CONFIGURATION					 0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW				 0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH				 0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0				 0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW				 0c1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH				 0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1				 0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW				 0c1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH				 0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2				 0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW				 0c1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH				 0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3				 0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW				 0c1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH				 0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4				 0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW				 0c1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH				 0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5				 0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW				 0c1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH				 0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6				 0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW				 0c1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH				 0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7				 0x1ef8
-
-/*
- * PCI Snoop Control
- */
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW				 0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH				 0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0				 0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW				 0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH			 0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1				 0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW				 0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH			 0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2				 0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW				 0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH			 0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3				 0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW				 0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH				 0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0				 0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW				 0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH			 0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1				 0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW				 0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH			 0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2				 0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW				 0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH			 0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3				 0x1fb8
-
-/*
- * PCI Configuration Address
- */
-
-#define PCI_0CONFIGURATION_ADDRESS				0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER		0xcfc
-#define PCI_1CONFIGURATION_ADDRESS				0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER		0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xcb4
-
-/*
- * PCI Error Report
- */
-
-#define PCI_0SERR_MASK						 0xc28
-#define PCI_0ERROR_ADDRESS_LOW					 0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH					 0x1d44
-#define PCI_0ERROR_DATA_LOW					 0x1d48
-#define PCI_0ERROR_DATA_HIGH					 0x1d4c
-#define PCI_0ERROR_COMMAND					 0x1d50
-#define PCI_0ERROR_CAUSE					 0x1d58
-#define PCI_0ERROR_MASK						 0x1d5c
-
-#define PCI_1SERR_MASK						 0xca8
-#define PCI_1ERROR_ADDRESS_LOW					 0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH					 0x1dc4
-#define PCI_1ERROR_DATA_LOW					 0x1dc8
-#define PCI_1ERROR_DATA_HIGH					 0x1dcc
-#define PCI_1ERROR_COMMAND					 0x1dd0
-#define PCI_1ERROR_CAUSE					 0x1dd8
-#define PCI_1ERROR_MASK						 0x1ddc
-
-
-/*
- * Lslave Debug	 (for internal use)
- */
-
-#define L_SLAVE_X0_ADDRESS					0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID				0x1d24
-#define L_SLAVE_X1_ADDRESS					0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID				0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW					0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH					0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE				0x1d60
-#define L_SLAVE_READ_DATA_LOW					0x1d38
-#define L_SLAVE_READ_DATA_HIGH					0x1d3c
-#define L_SLAVE_READ_ID						0x1d64
-
-#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */
-
-/*
- * PCI Configuration Function 0
- */
-
-#define PCI_DEVICE_AND_VENDOR_ID				0x000
-#define PCI_STATUS_AND_COMMAND					0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID				0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
-#define PCI_SCS_0_BASE_ADDRESS					0x010
-#define PCI_SCS_1_BASE_ADDRESS					0x014
-#define PCI_SCS_2_BASE_ADDRESS					0x018
-#define PCI_SCS_3_BASE_ADDRESS					0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID		0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER			0x030
-#define PCI_CAPABILTY_LIST_POINTER				0x034
-#define PCI_INTERRUPT_PIN_AND_LINE				0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY				0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL			0x044
-#define PCI_VPD_ADDRESS						0x048
-#define PCI_VPD_DATA						0X04c
-#define PCI_MSI_MESSAGE_CONTROL					0x050
-#define PCI_MSI_MESSAGE_ADDRESS					0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS				0x058
-#define PCI_MSI_MESSAGE_DATA					0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY			0x058
-
-/*
- * PCI Configuration Function 1
- */
-
-#define PCI_CS_0_BASE_ADDRESS					0x110
-#define PCI_CS_1_BASE_ADDRESS					0x114
-#define PCI_CS_2_BASE_ADDRESS					0x118
-#define PCI_CS_3_BASE_ADDRESS					0x11c
-#define PCI_BOOTCS_BASE_ADDRESS					0x120
-
-/*
- * PCI Configuration Function 2
- */
-
-#define PCI_P2P_MEM0_BASE_ADDRESS				0x210
-#define PCI_P2P_MEM1_BASE_ADDRESS				0x214
-#define PCI_P2P_I_O_BASE_ADDRESS				0x218
-#define PCI_CPU_BASE_ADDRESS					0x21c
-
-/*
- * PCI Configuration Function 4
- */
-
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW				0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH				0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW				0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH				0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW			0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH			0x424
-
-
-/*
- * PCI Configuration Function 5
- */
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW				0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH				0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW				0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH				0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW			0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH			0x524
-
-
-/*
- * PCI Configuration Function 6
- */
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW				0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH				0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW				0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH				0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW				0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH				0x624
-
-/*
- * PCI Configuration Function 7
- */
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW				0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH				0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW				0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH			0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW				0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH				0x724
-#endif
-
-/*
- * Interrupts
- */
-
-#define LOW_INTERRUPT_CAUSE_REGISTER				0xc18
-#define HIGH_INTERRUPT_CAUSE_REGISTER				0xc68
-#define CPU_INTERRUPT_MASK_REGISTER_LOW				0xc1c
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH			0xc6c
-#define CPU_SELECT_CAUSE_REGISTER				0xc70
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xc24
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xc64
-#define PCI_0SELECT_CAUSE					0xc74
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xca4
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xce4
-#define PCI_1SELECT_CAUSE					0xcf4
-#define CPU_INT_0_MASK						0xe60
-#define CPU_INT_1_MASK						0xe64
-#define CPU_INT_2_MASK						0xe68
-#define CPU_INT_3_MASK						0xe6c
-
-/*
- * I20 Support registers
- */
-
-#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE			0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE			0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE			0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE			0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE			0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE		0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE		0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE			0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE		0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE		0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE		0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE		0x044
-#define QUEUE_CONTROL_REGISTER_PCI0_SIDE			0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE			0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE		0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE		0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE		0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE		0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE		0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE		0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE		0x0F8
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE		0x0FC
-
-#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE			0x090
-#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE			0x094
-#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE			0x098
-#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE			0x09C
-#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE			0x0A0
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE		0x0A4
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE		0x0A8
-#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE			0x0AC
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE		0x0B0
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE		0x0B4
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE		0x0C0
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE		0x0C4
-#define QUEUE_CONTROL_REGISTER_PCI1_SIDE			0x0D0
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE			0x0D4
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0E0
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0E4
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0E8
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0EC
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0F0
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0F4
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE		0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE		0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE			0X1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE			0X1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE			0X1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE			0X1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE			0X1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE		0X1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE		0X1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE			0X1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE		0X1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE		0X1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE		0X1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE		0X1C44
-#define QUEUE_CONTROL_REGISTER_CPU0_SIDE			0X1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE			0X1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1CF8
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1CFC
-
-#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE			0X1C90
-#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE			0X1C94
-#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE			0X1C98
-#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE			0X1C9C
-#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE			0X1CA0
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE		0X1CA4
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE		0X1CA8
-#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE			0X1CAC
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE		0X1CB0
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE		0X1CB4
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE		0X1CC0
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE		0X1CC4
-#define QUEUE_CONTROL_REGISTER_CPU1_SIDE			0X1CD0
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE			0X1CD4
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CE0
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CE4
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CE8
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CEC
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CF0
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CF4
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1C7C
-
-/*
- * Communication Unit Registers
- */
-
-#define ETHERNET_0_ADDRESS_CONTROL_LOW
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH				0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS			0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW				0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH				0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS			0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW				0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH				0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS			0xf258
-#define MPSC_0_ADDRESS_CONTROL_LOW				0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH				0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS			0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS			0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW				0xf2a0
-#define MPSC_1_ADDRESS_CONTROL_HIGH				0xf2a4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS			0xf2a8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS			0xf2ac
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2b0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2b4
-#define MPSC_2_ADDRESS_CONTROL_LOW				0xf2c0
-#define MPSC_2_ADDRESS_CONTROL_HIGH				0xf2c4
-#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS			0xf2c8
-#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS			0xf2cc
-#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2d0
-#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2d4
-#define SERIAL_INIT_PCI_HIGH_ADDRESS				0xf320
-#define SERIAL_INIT_LAST_DATA					0xf324
-#define SERIAL_INIT_STATUS_AND_CONTROL				0xf328
-#define COMM_UNIT_ARBITER_CONTROL				0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT				0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE				0xf310
-#define COMM_UNIT_INTERRUPT_MASK				0xf314
-#define COMM_UNIT_ERROR_ADDRESS					0xf314
-
-/*
- * Cunit Debug	(for internal use)
- */
-
-#define CUNIT_ADDRESS						0xf340
-#define CUNIT_COMMAND_AND_ID					0xf344
-#define CUNIT_WRITE_DATA_LOW					0xf348
-#define CUNIT_WRITE_DATA_HIGH					0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE					0xf358
-#define CUNIT_READ_DATA_LOW					0xf350
-#define CUNIT_READ_DATA_HIGH					0xf354
-#define CUNIT_READ_ID						0xf35c
-
-/*
- * Fast Ethernet Unit Registers
- */
-
-/* Ethernet */
-
-#define ETHERNET_PHY_ADDRESS_REGISTER				0x2000
-#define ETHERNET_SMI_REGISTER					0x2010
-
-/* Ethernet 0 */
-
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER			0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER		0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER				0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER				0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER			0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER			0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER			0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER				0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER			0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER			0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0			0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1			0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2			0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3			0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0		0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1		0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2		0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3		0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0		0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1		0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE				0x2500
-
-/* Ethernet 1 */
-
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER			0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER		0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER				0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER				0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER			0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER			0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER			0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER				0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER			0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER			0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0			0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1			0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2			0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3			0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0		0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1		0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2		0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3		0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0		0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1		0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE				0x2900
-
-/* Ethernet 2 */
-
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER			0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER		0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER				0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER				0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER			0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER			0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER			0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER				0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER			0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER			0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0			0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1			0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2			0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3			0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0		0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1		0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2		0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3		0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0		0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1		0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE				0x2d00
-
-/*
- * SDMA Registers
- */
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER			0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER				0x4000
-#define CHANNEL0_COMMAND_REGISTER				0x4008
-#define CHANNEL0_RX_CMD_STATUS					0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES			0x4804
-#define CHANNEL0_RX_BUFFER_POINTER				0x4808
-#define CHANNEL0_RX_NEXT_POINTER				0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER			0x4810
-#define CHANNEL0_TX_CMD_STATUS					0x4C00
-#define CHANNEL0_TX_PACKET_SIZE					0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER				0x4C08
-#define CHANNEL0_TX_NEXT_POINTER				0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER			0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER			0x4c14
-#define CHANNEL1_CONFIGURATION_REGISTER				0x6000
-#define CHANNEL1_COMMAND_REGISTER				0x6008
-#define CHANNEL1_RX_CMD_STATUS					0x6800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES			0x6804
-#define CHANNEL1_RX_BUFFER_POINTER				0x6808
-#define CHANNEL1_RX_NEXT_POINTER				0x680c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER			0x6810
-#define CHANNEL1_TX_CMD_STATUS					0x6C00
-#define CHANNEL1_TX_PACKET_SIZE					0x6C04
-#define CHANNEL1_TX_BUFFER_POINTER				0x6C08
-#define CHANNEL1_TX_NEXT_POINTER				0x6C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER			0x6810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER			0x6c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER			0x6c14
-
-/* SDMA Interrupt */
-
-#define SDMA_CAUSE						0xb820
-#define SDMA_MASK						0xb8a0
-
-
-/*
- * Baude Rate Generators Registers
- */
-
-/* BRG 0 */
-
-#define BRG0_CONFIGURATION_REGISTER				0xb200
-#define BRG0_BAUDE_TUNING_REGISTER				0xb204
-
-/* BRG 1 */
-
-#define BRG1_CONFIGURATION_REGISTER				0xb208
-#define BRG1_BAUDE_TUNING_REGISTER				0xb20c
-
-/* BRG 2 */
-
-#define BRG2_CONFIGURATION_REGISTER				0xb210
-#define BRG2_BAUDE_TUNING_REGISTER				0xb214
-
-/* BRG Interrupts */
-
-#define BRG_CAUSE_REGISTER					0xb834
-#define BRG_MASK_REGISTER					0xb8b4
-
-/* MISC */
-
-#define MAIN_ROUTING_REGISTER					0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER				0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER				0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER		0xb40c
-#define WATCHDOG_CONFIGURATION_REGISTER				0xb410
-#define WATCHDOG_VALUE_REGISTER					0xb414
-
-
-/*
- * Flex TDM Registers
- */
-
-/* FTDM Port */
-
-#define FLEXTDM_TRANSMIT_READ_POINTER				0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER				0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER				0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER			0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER			0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER			0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER			0xa818
-
-/* FTDM Interrupts */
-
-#define FTDM_CAUSE_REGISTER					0xb830
-#define FTDM_MASK_REGISTER					0xb8b0
-
-
-/*
- * GPP Interface Registers
- */
-
-#define GPP_IO_CONTROL						0xf100
-#define GPP_LEVEL_CONTROL					0xf110
-#define GPP_VALUE						0xf104
-#define GPP_INTERRUPT_CAUSE					0xf108
-#define GPP_INTERRUPT_MASK					0xf10c
-
-#define MPP_CONTROL0						0xf000
-#define MPP_CONTROL1						0xf004
-#define MPP_CONTROL2						0xf008
-#define MPP_CONTROL3						0xf00c
-#define DEBUG_PORT_MULTIPLEX					0xf014
-#define SERIAL_PORT_MULTIPLEX					0xf010
-
-/*
- * I2C Registers
- */
-
-#define I2C_SLAVE_ADDRESS					0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS				0xc040
-#define I2C_DATA						0xc004
-#define I2C_CONTROL						0xc008
-#define I2C_STATUS_BAUDE_RATE					0xc00C
-#define I2C_SOFT_RESET						0xc01c
-
-/*
- * MPSC Registers
- */
-
-/*
- * MPSC0
- */
-
-#define MPSC0_MAIN_CONFIGURATION_LOW				0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH				0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION				0x8008
-#define CHANNEL0_REGISTER1					0x800c
-#define CHANNEL0_REGISTER2					0x8010
-#define CHANNEL0_REGISTER3					0x8014
-#define CHANNEL0_REGISTER4					0x8018
-#define CHANNEL0_REGISTER5					0x801c
-#define CHANNEL0_REGISTER6					0x8020
-#define CHANNEL0_REGISTER7					0x8024
-#define CHANNEL0_REGISTER8					0x8028
-#define CHANNEL0_REGISTER9					0x802c
-#define CHANNEL0_REGISTER10					0x8030
-#define CHANNEL0_REGISTER11					0x8034
-
-/*
- * MPSC1
- */
-
-#define MPSC1_MAIN_CONFIGURATION_LOW				0x9000
-#define MPSC1_MAIN_CONFIGURATION_HIGH				0x9004
-#define MPSC1_PROTOCOL_CONFIGURATION				0x9008
-#define CHANNEL1_REGISTER1					0x900c
-#define CHANNEL1_REGISTER2					0x9010
-#define CHANNEL1_REGISTER3					0x9014
-#define CHANNEL1_REGISTER4					0x9018
-#define CHANNEL1_REGISTER5					0x901c
-#define CHANNEL1_REGISTER6					0x9020
-#define CHANNEL1_REGISTER7					0x9024
-#define CHANNEL1_REGISTER8					0x9028
-#define CHANNEL1_REGISTER9					0x902c
-#define CHANNEL1_REGISTER10					0x9030
-#define CHANNEL1_REGISTER11					0x9034
-
-/*
- * MPSCs Interupts
- */
-
-#define MPSC0_CAUSE						0xb804
-#define MPSC0_MASK						0xb884
-#define MPSC1_CAUSE						0xb80c
-#define MPSC1_MASK						0xb88c
-
-#endif	/* __ASM_MIPS_MV64240_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 918a4894b58..6a5fa32f615 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -172,6 +172,7 @@ ASMMACRO(tlb_probe_hazard,
 	 nop; nop; nop
 	)
 ASMMACRO(irq_enable_hazard,
+	 _ssnop; _ssnop; _ssnop;
 	)
 ASMMACRO(irq_disable_hazard,
 	nop; nop; nop
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
index 92f6c36aac4..5097cbf183a 100644
--- a/include/asm-mips/ioctls.h
+++ b/include/asm-mips/ioctls.h
@@ -77,6 +77,10 @@
 #define TIOCSBRK	0x5427  /* BSD compatibility */
 #define TIOCCBRK	0x5428  /* BSD compatibility */
 #define TIOCGSID	0x7416  /* Return the session ID of FD */
+#define TCGETS2		_IOR('T',0x2A, struct termios2)
+#define TCSETS2		_IOW('T',0x2B, struct termios2)
+#define TCSETSW2	_IOW('T',0x2C, struct termios2)
+#define TCSETSF2	_IOW('T',0x2D, struct termios2)
 #define TIOCGPTN	_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK	_IOW('T',0x31, int)  /* Lock/unlock Pty */
 
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 97102ebc54b..2cb52cf8bd4 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,7 +24,30 @@ static inline int irq_canonicalize(int irq)
 #define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
 #endif
 
+#ifdef CONFIG_MIPS_MT_SMTC
+
+struct irqaction;
+
+extern unsigned long irq_hwmask[];
+extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
+                          unsigned long hwmask);
+
+static inline void smtc_im_ack_irq(unsigned int irq)
+{
+	if (irq_hwmask[irq] & ST0_IM)
+		set_c0_status(irq_hwmask[irq] & ST0_IM);
+}
+
+#else
+
+static inline void smtc_im_ack_irq(unsigned int irq)
+{
+}
+
+#endif /* CONFIG_MIPS_MT_SMTC */
+
 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
+
 /*
  * Clear interrupt mask handling "backstop" if irq_hwmask
  * entry so indicates. This implies that the ack() or end()
@@ -38,6 +61,7 @@ do {									\
 		                   ~(irq_hwmask[irq] & 0x0000ff00));	\
 } while (0)
 #else
+
 #define __DO_IRQ_SMTC_HOOK(irq) do { } while (0)
 #endif
 
@@ -60,14 +84,6 @@ do {									\
 extern void arch_init_irq(void);
 extern void spurious_interrupt(void);
 
-#ifdef CONFIG_MIPS_MT_SMTC
-struct irqaction;
-
-extern unsigned long irq_hwmask[];
-extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
-                          unsigned long hwmask);
-#endif /* CONFIG_MIPS_MT_SMTC */
-
 extern int allocate_irqno(void);
 extern void alloc_legacy_irqno(void);
 extern void free_irqno(unsigned int irq);
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 958e29706e2..b2dc35f5618 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -13,6 +13,7 @@
 #include <asm/jmr3927/tx3927.h>
 #include <asm/addrspace.h>
 #include <asm/system.h>
+#include <asm/txx9irq.h>
 
 /* CS */
 #define JMR3927_ROMCE0	0x1fc00000	/* 4M */
@@ -115,7 +116,7 @@
 #define JMR3927_NR_IRQ_IRC	16	/* On-Chip IRC */
 #define JMR3927_NR_IRQ_IOC	8	/* PCI/MODEM/INT[6:7] */
 
-#define JMR3927_IRQ_IRC	16
+#define JMR3927_IRQ_IRC	TXX9_IRQ_BASE
 #define JMR3927_IRQ_IOC	(JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
 #define JMR3927_IRQ_END	(JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
 
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 0b9073bfb75..4be2f25f70d 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -50,21 +50,6 @@ struct tx3927_dma_reg {
 	volatile unsigned long unused0;
 };
 
-struct tx3927_irc_reg {
-	volatile unsigned long cer;
-	volatile unsigned long cr[2];
-	volatile unsigned long unused0;
-	volatile unsigned long ilr[8];
-	volatile unsigned long unused1[4];
-	volatile unsigned long imr;
-	volatile unsigned long unused2[7];
-	volatile unsigned long scr;
-	volatile unsigned long unused3[7];
-	volatile unsigned long ssr;
-	volatile unsigned long unused4[7];
-	volatile unsigned long csr;
-};
-
 #include <asm/byteorder.h>
 
 #ifdef __BIG_ENDIAN
@@ -225,26 +210,6 @@ struct tx3927_ccfg_reg {
 /*
  * IRC
  */
-#define TX3927_IR_MAX_LEVEL	7
-
-/* IRCER : Int. Control Enable */
-#define TX3927_IRCER_ICE	0x00000001
-
-/* IRCR : Int. Control */
-#define TX3927_IRCR_LOW	0x00000000
-#define TX3927_IRCR_HIGH	0x00000001
-#define TX3927_IRCR_DOWN	0x00000002
-#define TX3927_IRCR_UP	0x00000003
-
-/* IRSCR : Int. Status Control */
-#define TX3927_IRSCR_EIClrE	0x00000100
-#define TX3927_IRSCR_EIClr_MASK	0x0000000f
-
-/* IRCSR : Int. Current Status */
-#define TX3927_IRCSR_IF	0x00010000
-#define TX3927_IRCSR_ILV_MASK	0x00000700
-#define TX3927_IRCSR_IVL_MASK	0x0000001f
-
 #define TX3927_IR_INT0	0
 #define TX3927_IR_INT1	1
 #define TX3927_IR_INT2	2
@@ -347,7 +312,6 @@ struct tx3927_ccfg_reg {
 #define tx3927_sdramcptr	((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
 #define tx3927_romcptr		((struct tx3927_romc_reg *)TX3927_ROMC_REG)
 #define tx3927_dmaptr		((struct tx3927_dma_reg *)TX3927_DMA_REG)
-#define tx3927_ircptr		((struct tx3927_irc_reg *)TX3927_IRC_REG)
 #define tx3927_pcicptr		((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
 #define tx3927_ccfgptr		((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
 #define tx3927_tmrptr(ch)	((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
index ed882c88e0c..f9a5ce5c9af 100644
--- a/include/asm-mips/local.h
+++ b/include/asm-mips/local.h
@@ -4,6 +4,7 @@
 #include <linux/percpu.h>
 #include <linux/bitops.h>
 #include <asm/atomic.h>
+#include <asm/cmpxchg.h>
 #include <asm/war.h>
 
 typedef struct
@@ -114,68 +115,6 @@ static __inline__ long local_sub_return(long i, local_t * l)
 	return result;
 }
 
-/*
- * local_sub_if_positive - conditionally subtract integer from atomic variable
- * @i: integer value to subtract
- * @l: pointer of type local_t
- *
- * Atomically test @l and subtract @i if @l is greater or equal than @i.
- * The function returns the old value of @l minus @i.
- */
-static __inline__ long local_sub_if_positive(long i, local_t * l)
-{
-	unsigned long result;
-
-	if (cpu_has_llsc && R10000_LLSC_WAR) {
-		unsigned long temp;
-
-		__asm__ __volatile__(
-		"	.set	mips3					\n"
-		"1:"	__LL	"%1, %2		# local_sub_if_positive\n"
-		"	dsubu	%0, %1, %3				\n"
-		"	bltz	%0, 1f					\n"
-			__SC	"%0, %2					\n"
-		"	.set	noreorder				\n"
-		"	beqzl	%0, 1b					\n"
-		"	 dsubu	%0, %1, %3				\n"
-		"	.set	reorder					\n"
-		"1:							\n"
-		"	.set	mips0					\n"
-		: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
-		: "Ir" (i), "m" (l->a.counter)
-		: "memory");
-	} else if (cpu_has_llsc) {
-		unsigned long temp;
-
-		__asm__ __volatile__(
-		"	.set	mips3					\n"
-		"1:"	__LL	"%1, %2		# local_sub_if_positive\n"
-		"	dsubu	%0, %1, %3				\n"
-		"	bltz	%0, 1f					\n"
-			__SC	"%0, %2					\n"
-		"	.set	noreorder				\n"
-		"	beqz	%0, 1b					\n"
-		"	 dsubu	%0, %1, %3				\n"
-		"	.set	reorder					\n"
-		"1:							\n"
-		"	.set	mips0					\n"
-		: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
-		: "Ir" (i), "m" (l->a.counter)
-		: "memory");
-	} else {
-		unsigned long flags;
-
-		local_irq_save(flags);
-		result = l->a.counter;
-		result -= i;
-		if (result >= 0)
-			l->a.counter = result;
-		local_irq_restore(flags);
-	}
-
-	return result;
-}
-
 #define local_cmpxchg(l, o, n) \
 	((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
 #define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n)))
@@ -234,12 +173,6 @@ static __inline__ long local_sub_if_positive(long i, local_t * l)
 #define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
 
 /*
- * local_dec_if_positive - decrement by 1 if old value positive
- * @l: pointer of type local_t
- */
-#define local_dec_if_positive(l)	local_sub_if_positive(1, l)
-
-/*
  * local_add_negative - add and test if negative
  * @l: pointer of type local_t
  * @i: integer value to add
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 6eba2e576aa..a77128362a7 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -33,13 +33,24 @@ static __inline__ int ide_probe_legacy(void)
 {
 #ifdef CONFIG_PCI
 	struct pci_dev *dev;
-	if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
-	    (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
-		pci_dev_put(dev);
-
-		return 1;
-	}
+	/*
+	 * This can be called on the ide_setup() path, super-early in
+	 * boot.  But the down_read() will enable local interrupts,
+	 * which can cause some machines to crash.  So here we detect
+	 * and flag that situation and bail out early.
+	 */
+	if (no_pci_devices())
+		return 0;
+	dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
+	if (dev)
+		goto found;
+	dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
+	if (dev)
+		goto found;
 	return 0;
+found:
+	pci_dev_put(dev);
+	return 1;
 #elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
 	return 1;
 #else
@@ -49,48 +60,42 @@ static __inline__ int ide_probe_legacy(void)
 
 static __inline__ int ide_default_irq(unsigned long base)
 {
-	if (ide_probe_legacy())
-		switch (base) {
-		case 0x1f0:
-			return 14;
-		case 0x170:
-			return 15;
-		case 0x1e8:
-			return 11;
-		case 0x168:
-			return 10;
-		case 0x1e0:
-			return 8;
-		case 0x160:
-			return 12;
+	switch (base) {
+		case 0x1f0: return 14;
+		case 0x170: return 15;
+		case 0x1e8: return 11;
+		case 0x168: return 10;
+		case 0x1e0: return 8;
+		case 0x160: return 12;
 		default:
 			return 0;
-		}
-	else
-		return 0;
+	}
 }
 
 static __inline__ unsigned long ide_default_io_base(int index)
 {
-	if (ide_probe_legacy())
+	if (!ide_probe_legacy())
+		return 0;
+	/*
+	 *      If PCI is present then it is not safe to poke around
+	 *      the other legacy IDE ports. Only 0x1f0 and 0x170 are
+	 *      defined compatibility mode ports for PCI. A user can
+	 *      override this using ide= but we must default safe.
+	 */
+	if (no_pci_devices()) {
 		switch (index) {
-		case 0:
-			return 0x1f0;
-		case 1:
-			return 0x170;
-		case 2:
-			return 0x1e8;
-		case 3:
-			return 0x168;
-		case 4:
-			return 0x1e0;
-		case 5:
-			return 0x160;
-		default:
-			return 0;
+		case 2: return 0x1e8;
+		case 3: return 0x168;
+		case 4: return 0x1e0;
+		case 5: return 0x160;
 		}
-	else
+	}
+	switch (index) {
+	case 0: return 0x1f0;
+	case 1: return 0x170;
+	default:
 		return 0;
+	}
 }
 
 #define IDE_ARCH_OBSOLETE_INIT
diff --git a/include/asm-mips/mach-ocelot/mach-gt64120.h b/include/asm-mips/mach-ocelot/mach-gt64120.h
deleted file mode 100644
index a62ecb53c75..00000000000
--- a/include/asm-mips/mach-ocelot/mach-gt64120.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
-#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
-
-/*
- * PCI address allocation
- */
-#define GT_PCI_MEM_BASE	(0x22000000UL)
-#define GT_PCI_MEM_SIZE	GT_DEF_PCI0_MEM0_SIZE
-#define GT_PCI_IO_BASE	(0x20000000UL)
-#define GT_PCI_IO_SIZE	GT_DEF_PCI0_IO_SIZE
-
-extern unsigned long gt64120_base;
-
-#define GT64120_BASE	(gt64120_base)
-
-/*
- * GT timer irq
- */
-#define	GT_TIMER		6
-
-#endif  /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h
deleted file mode 100644
index b6144bafc56..00000000000
--- a/include/asm-mips/marvell.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- */
-#ifndef __ASM_MIPS_MARVELL_H
-#define __ASM_MIPS_MARVELL_H
-
-#include <linux/pci.h>
-
-#include <asm/byteorder.h>
-
-extern unsigned long marvell_base;
-
-/*
- * Because of an error/peculiarity in the Galileo chip, we need to swap the
- * bytes when running bigendian.
- */
-#define __MV_READ(ofs)							\
-	(*(volatile u32 *)(marvell_base+(ofs)))
-#define __MV_WRITE(ofs, data)						\
-	do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0)
-
-#define MV_READ(ofs)		le32_to_cpu(__MV_READ(ofs))
-#define MV_WRITE(ofs, data)	__MV_WRITE(ofs, cpu_to_le32(data))
-
-#define MV_READ_16(ofs)							\
-        le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs)))
-#define MV_WRITE_16(ofs, data)  \
-        *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data)
-
-#define MV_READ_8(ofs)							\
-	*(volatile u8 *)(marvell_base+(ofs))
-#define MV_WRITE_8(ofs, data)						\
-	*(volatile u8 *)(marvell_base+(ofs)) = data
-
-#define MV_SET_REG_BITS(ofs, bits)					\
-	(*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits))
-#define MV_RESET_REG_BITS(ofs, bits)					\
-	(*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits))
-
-extern struct pci_ops mv_pci_ops;
-
-struct mv_pci_controller {
-	struct pci_controller   pcic;
-
-	/*
-	 * GT-64240/MV-64340 specific, per host bus information
-	 */
-	unsigned long   config_addr;
-	unsigned long   config_vreg;
-};
-
-extern void ll_mv64340_irq(void);
-extern void mv64340_irq_init(unsigned int base);
-
-#endif	/* __ASM_MIPS_MARVELL_H */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index b92dd8c760d..e3301e54d55 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -142,7 +142,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 /*
  * __pa()/__va() should be used only during mem init.
  */
-#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
+#ifdef CONFIG_64BIT
 #define __pa(x)								\
 ({									\
     unsigned long __x = (unsigned long)(x);				\
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 2fbd47eba32..59c865deb0c 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  */
 
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGDIR_SHIFT	21
-#else
-#define PGDIR_SHIFT	22
-#endif
+#define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 
@@ -55,17 +51,11 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  * Entries per page directory level: we use two-level, so
  * we don't really have any PUD/PMD directory physically.
  */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGD_ORDER	1
+#define __PGD_ORDER	(32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
+#define PGD_ORDER	(__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
 #define PUD_ORDER	aieeee_attempt_to_allocate_pud
 #define PMD_ORDER	1
 #define PTE_ORDER	0
-#else
-#define PGD_ORDER	0
-#define PUD_ORDER	aieeee_attempt_to_allocate_pud
-#define PMD_ORDER	1
-#define PTE_ORDER	0
-#endif
 
 #define PTRS_PER_PGD	((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
 #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 2e2d70d13ff..d2ee2815674 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -168,11 +168,15 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
 #define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
 #endif
 
-#define PGD_T_LOG2	ffz(~sizeof(pgd_t))
-#define PMD_T_LOG2	ffz(~sizeof(pmd_t))
-#define PTE_T_LOG2	ffz(~sizeof(pte_t))
+#define PGD_T_LOG2	(__builtin_ffs(sizeof(pgd_t)) - 1)
+#define PMD_T_LOG2	(__builtin_ffs(sizeof(pmd_t)) - 1)
+#define PTE_T_LOG2	(__builtin_ffs(sizeof(pte_t)) - 1)
 
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+/*
+ * We used to declare this array with size but gcc 3.3 and older are not able
+ * to find that this expression is a constant, so the size is dropped.
+ */
+extern pgd_t swapper_pg_dir[];
 
 /*
  * The following only work if pte_present() is true.
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
index 2738c1366f6..c34d36b6b8c 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -227,10 +227,15 @@
 	(A_BCM1480_DUART(chan) +					\
 	 BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
 
+#define DUART_IMRISR_SPACING	    0x20
+#define DUART_INCHNG_SPACING	    0x10
+
 #define R_BCM1480_DUART_IMRREG(chan)					\
 	(R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
 #define R_BCM1480_DUART_ISRREG(chan)					\
 	(R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_INCHREG(chan)					\
+	(R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING)
 
 #define A_BCM1480_DUART_IMRREG(chan)					\
 	(A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adecf..ff3e8936b49 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
 
 #define PARKED_INDEX	((unsigned int)0x80000000)
 
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
 #endif /*  _ASM_SMTC_MT_H */
diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
index 07f873351a8..0bf82818aa5 100644
--- a/include/asm-mips/stacktrace.h
+++ b/include/asm-mips/stacktrace.h
@@ -9,7 +9,11 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
 				  unsigned long pc, unsigned long *ra);
 #else
 #define raw_show_trace 1
-#define unwind_stack(task, sp, pc, ra)	0
+static inline unsigned long unwind_stack(struct task_struct *task,
+	unsigned long *sp, unsigned long pc, unsigned long *ra)
+{
+	return 0;
+}
 #endif
 
 static __always_inline void prepare_frametrace(struct pt_regs *regs)
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 357251f4251..480b574e248 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -17,6 +17,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/barrier.h>
+#include <asm/cmpxchg.h>
 #include <asm/cpu-features.h>
 #include <asm/dsp.h>
 #include <asm/war.h>
@@ -194,266 +195,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
-#define __HAVE_ARCH_CMPXCHG 1
-
-static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
-	unsigned long new)
-{
-	__u32 retval;
-
-	if (cpu_has_llsc && R10000_LLSC_WAR) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	.set	mips0					\n"
-		"	move	$1, %z4					\n"
-		"	.set	mips3					\n"
-		"	sc	$1, %1					\n"
-		"	beqzl	$1, 1b					\n"
-		"2:							\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else if (cpu_has_llsc) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	.set	mips0					\n"
-		"	move	$1, %z4					\n"
-		"	.set	mips3					\n"
-		"	sc	$1, %1					\n"
-		"	beqz	$1, 3f					\n"
-		"2:							\n"
-		"	.subsection 2					\n"
-		"3:	b	1b					\n"
-		"	.previous					\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else {
-		unsigned long flags;
-
-		raw_local_irq_save(flags);
-		retval = *m;
-		if (retval == old)
-			*m = new;
-		raw_local_irq_restore(flags);	/* implies memory barrier  */
-	}
-
-	smp_llsc_mb();
-
-	return retval;
-}
-
-static inline unsigned long __cmpxchg_u32_local(volatile int * m,
-	unsigned long old, unsigned long new)
-{
-	__u32 retval;
-
-	if (cpu_has_llsc && R10000_LLSC_WAR) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	.set	mips0					\n"
-		"	move	$1, %z4					\n"
-		"	.set	mips3					\n"
-		"	sc	$1, %1					\n"
-		"	beqzl	$1, 1b					\n"
-		"2:							\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else if (cpu_has_llsc) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	.set	mips0					\n"
-		"	move	$1, %z4					\n"
-		"	.set	mips3					\n"
-		"	sc	$1, %1					\n"
-		"	beqz	$1, 1b					\n"
-		"2:							\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else {
-		unsigned long flags;
-
-		local_irq_save(flags);
-		retval = *m;
-		if (retval == old)
-			*m = new;
-		local_irq_restore(flags);	/* implies memory barrier  */
-	}
-
-	return retval;
-}
-
-#ifdef CONFIG_64BIT
-static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
-	unsigned long new)
-{
-	__u64 retval;
-
-	if (cpu_has_llsc && R10000_LLSC_WAR) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	move	$1, %z4					\n"
-		"	scd	$1, %1					\n"
-		"	beqzl	$1, 1b					\n"
-		"2:							\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else if (cpu_has_llsc) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	move	$1, %z4					\n"
-		"	scd	$1, %1					\n"
-		"	beqz	$1, 3f					\n"
-		"2:							\n"
-		"	.subsection 2					\n"
-		"3:	b	1b					\n"
-		"	.previous					\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else {
-		unsigned long flags;
-
-		raw_local_irq_save(flags);
-		retval = *m;
-		if (retval == old)
-			*m = new;
-		raw_local_irq_restore(flags);	/* implies memory barrier  */
-	}
-
-	smp_llsc_mb();
-
-	return retval;
-}
-
-static inline unsigned long __cmpxchg_u64_local(volatile int * m,
-	unsigned long old, unsigned long new)
-{
-	__u64 retval;
-
-	if (cpu_has_llsc && R10000_LLSC_WAR) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	move	$1, %z4					\n"
-		"	scd	$1, %1					\n"
-		"	beqzl	$1, 1b					\n"
-		"2:							\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else if (cpu_has_llsc) {
-		__asm__ __volatile__(
-		"	.set	push					\n"
-		"	.set	noat					\n"
-		"	.set	mips3					\n"
-		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
-		"	bne	%0, %z3, 2f				\n"
-		"	move	$1, %z4					\n"
-		"	scd	$1, %1					\n"
-		"	beqz	$1, 1b					\n"
-		"2:							\n"
-		"	.set	pop					\n"
-		: "=&r" (retval), "=R" (*m)
-		: "R" (*m), "Jr" (old), "Jr" (new)
-		: "memory");
-	} else {
-		unsigned long flags;
-
-		local_irq_save(flags);
-		retval = *m;
-		if (retval == old)
-			*m = new;
-		local_irq_restore(flags);	/* implies memory barrier  */
-	}
-
-	return retval;
-}
-
-#else
-extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
-	volatile int * m, unsigned long old, unsigned long new);
-#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
-extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels(
-	volatile int * m, unsigned long old, unsigned long new);
-#define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels
-#endif
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid cmpxchg().  */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
-	unsigned long new, int size)
-{
-	switch (size) {
-	case 4:
-		return __cmpxchg_u32(ptr, old, new);
-	case 8:
-		return __cmpxchg_u64(ptr, old, new);
-	}
-	__cmpxchg_called_with_bad_pointer();
-	return old;
-}
-
-static inline unsigned long __cmpxchg_local(volatile void * ptr,
-	unsigned long old, unsigned long new, int size)
-{
-	switch (size) {
-	case 4:
-		return __cmpxchg_u32_local(ptr, old, new);
-	case 8:
-		return __cmpxchg_u64_local(ptr, old, new);
-	}
-	__cmpxchg_called_with_bad_pointer();
-	return old;
-}
-
-#define cmpxchg(ptr,old,new) \
-	((__typeof__(*(ptr)))__cmpxchg((ptr), \
-		(unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
-
-#define cmpxchg_local(ptr,old,new) \
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
-		(unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
-
 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
 
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h
index 5bfdc3b6451..c83c68444e8 100644
--- a/include/asm-mips/termbits.h
+++ b/include/asm-mips/termbits.h
@@ -164,6 +164,7 @@ struct ktermios {
 #define HUPCL	0002000		/* Hang up on last close.  */
 #define CLOCAL	0004000		/* Ignore modem status lines.  */
 #define CBAUDEX 0010000
+#define    BOTHER 0010000
 #define    B57600 0010001
 #define   B115200 0010002
 #define   B230400 0010003
@@ -179,9 +180,11 @@ struct ktermios {
 #define  B3000000 0010015
 #define  B3500000 0010016
 #define  B4000000 0010017
-#define CIBAUD	  002003600000	/* input baud rate (not used) */
+#define CIBAUD	  002003600000	/* input baud rate */
 #define CMSPAR    010000000000	/* mark or space (stick) parity */
-#define CRTSCTS	  020000000000		/* flow control */
+#define CRTSCTS	  020000000000	/* flow control */
+
+#define IBSHIFT	16		/* Shift from CBAUD to CIBAUD */
 
 /* c_lflag bits */
 #define ISIG	0000001		/* Enable signals.  */
diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h
index 2ce07f4be36..a275661fa7e 100644
--- a/include/asm-mips/termios.h
+++ b/include/asm-mips/termios.h
@@ -122,8 +122,10 @@ struct termio {
 	copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
 })
 
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
 
 #endif /* defined(__KERNEL__) */
 
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a86777..a60649569c2 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
 
 
 #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
-#define RBTX4927_RTL_8019_IRQ  (29)
+#define RBTX4927_RTL_8019_IRQ  (TX4927_IRQ_PIC_BEG + 5)
 
 int toshiba_rbtx4927_irq_nested(int sw_irq);
 
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f..4bd4368e188 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
 #define __ASM_TX4927_TX4927_H
 
 #include <asm/tx4927/tx4927_mips.h>
+#include <asm/txx9irq.h>
 
 /*
  This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
 #define TX4927_PIO_LIMIT                0xf50f
 
 
-/* TX4927 Interrupt Controller (32-bit registers) */
-#define TX4927_IRC_BASE                 0xf510
-#define TX4927_IRC_IRFLAG0              0xf510
-#define TX4927_IRC_IRFLAG1              0xf514
-#define TX4927_IRC_IRPOL                0xf518
-#define TX4927_IRC_IRRCNT               0xf51c
-#define TX4927_IRC_IRMASKINT            0xf520
-#define TX4927_IRC_IRMASKEXT            0xf524
-#define TX4927_IRC_IRDEN                0xf600
-#define TX4927_IRC_IRDM0                0xf604
-#define TX4927_IRC_IRDM1                0xf608
-#define TX4927_IRC_IRLVL0               0xf610
-#define TX4927_IRC_IRLVL1               0xf614
-#define TX4927_IRC_IRLVL2               0xf618
-#define TX4927_IRC_IRLVL3               0xf61c
-#define TX4927_IRC_IRLVL4               0xf620
-#define TX4927_IRC_IRLVL5               0xf624
-#define TX4927_IRC_IRLVL6               0xf628
-#define TX4927_IRC_IRLVL7               0xf62c
-#define TX4927_IRC_IRMSK                0xf640
-#define TX4927_IRC_IREDC                0xf660
-#define TX4927_IRC_IRPND                0xf680
-#define TX4927_IRC_IRCS                 0xf6a0
-#define TX4927_IRC_LIMIT                0xf6ff
-
-
 /* TX4927 AC-link controller (32-bit registers) */
 #define TX4927_ACLC_BASE                0xf700
 #define TX4927_ACLC_ACCTLEN             0xf700
@@ -493,25 +468,11 @@
 #define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
 
 
+#define TX4927_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4927_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-
-
-#define MI8259_IRQ_ISA_RAW_BEG   0    /* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4927_IRQ_CP0_RAW_BEG   0    /* tx4927 cpu built-in cp0 */
-#define TX4927_IRQ_CP0_RAW_END   7
-#define TX4927_IRQ_PIC_RAW_BEG   0    /* tx4927 cpu build-in pic */
-#define TX4927_IRQ_PIC_RAW_END  31
-
-
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG   /*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END   /* 15 */
-
-#define TX4927_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG)  /* 16 */
-#define TX4927_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END)  /* 23 */
-
-#define TX4927_IRQ_PIC_BEG  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG)  /* 24 */
-#define TX4927_IRQ_PIC_END  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END)  /* 55 */
+#define TX4927_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4927_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 
 
 #define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f4..f98b2bb719d 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
 #define TX4927_PCI_CLK_ACK      0x04
 #define TX4927_PCI_CLK_ACE      0x02
 #define TX4927_PCI_CLK_ENDIAN   0x01
-#define TX4927_NR_IRQ_LOCAL     (8+16)
+#define TX4927_NR_IRQ_LOCAL     TX4927_IRQ_PIC_BEG
 #define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
 
 #define TX4927_IR_PCIC  	16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
         volatile unsigned long long ramp;
 };
 
-struct tx4927_irc_reg {
-        volatile unsigned long cer;
-        volatile unsigned long cr[2];
-        volatile unsigned long unused0;
-        volatile unsigned long ilr[8];
-        volatile unsigned long unused1[4];
-        volatile unsigned long imr;
-        volatile unsigned long unused2[7];
-        volatile unsigned long scr;
-        volatile unsigned long unused3[7];
-        volatile unsigned long ssr;
-        volatile unsigned long unused4[7];
-        volatile unsigned long csr;
-};
-
 struct tx4927_pcic_reg {
         volatile unsigned long pciid;
         volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
-/* IRCSR : Int. Current Status */
-#define TX4927_IRCSR_IF         0x00010000
-#define TX4927_IRCSR_ILV_MASK   0x00000700
-#define TX4927_IRCSR_IVL_MASK   0x0000001f
-
 /*
  * PCIC
  */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
 #define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
 #define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
 #define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
-#define tx4927_ircptr           ((struct tx4927_irc_reg *)TX4927_IRC_REG)
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 74e7d8061e5..b14acb575be 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -14,6 +14,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/tx4938/tx4938.h>
+#include <asm/txx9irq.h>
 
 /* CS */
 #define RBTX4938_CE0	0x1c000000	/* 64M */
@@ -123,21 +124,11 @@
 #define RBTX4938_NR_IRQ_IRC	32	/* On-Chip IRC */
 #define RBTX4938_NR_IRQ_IOC	8
 
-#define MI8259_IRQ_ISA_RAW_BEG   0	/* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4938_IRQ_CP0_RAW_BEG   0	/* tx4938 cpu built-in cp0 */
-#define TX4938_IRQ_CP0_RAW_END   7
-#define TX4938_IRQ_PIC_RAW_BEG   0	/* tx4938 cpu build-in pic */
-#define TX4938_IRQ_PIC_RAW_END  31
+#define TX4938_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4938_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG	/*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END	/* 15 */
-
-#define TX4938_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG)	/* 16 */
-#define TX4938_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END)	/* 23 */
-
-#define TX4938_IRQ_PIC_BEG  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG)	/* 24 */
-#define TX4938_IRQ_PIC_END  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END)	/* 55 */
+#define TX4938_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4938_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 #define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
 #define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
 #define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
@@ -192,10 +183,4 @@
 #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
 #define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
 
-/* IRCR : Int. Control */
-#define TX4938_IRCR_LOW  0x00000000
-#define TX4938_IRCR_HIGH 0x00000001
-#define TX4938_IRCR_DOWN 0x00000002
-#define TX4938_IRCR_UP   0x00000003
-
 #endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index e25b1a0975c..afdb19813ca 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -272,20 +272,6 @@ struct tx4938_pio_reg {
 	volatile unsigned long maskcpu;
 	volatile unsigned long maskext;
 };
-struct tx4938_irc_reg {
-	volatile unsigned long cer;
-	volatile unsigned long cr[2];
-	volatile unsigned long unused0;
-	volatile unsigned long ilr[8];
-	volatile unsigned long unused1[4];
-	volatile unsigned long imr;
-	volatile unsigned long unused2[7];
-	volatile unsigned long scr;
-	volatile unsigned long unused3[7];
-	volatile unsigned long ssr;
-	volatile unsigned long unused4[7];
-	volatile unsigned long csr;
-};
 
 struct tx4938_ndfmc_reg {
 	endian_def_l2(unused0, dtr);
@@ -646,39 +632,12 @@ struct tx4938_ccfg_reg {
 #define TX4938_DMA_CSR_DESERR	0x00000002
 #define TX4938_DMA_CSR_SORERR	0x00000001
 
-/* TX4938 Interrupt Controller (32-bit registers) */
-#define TX4938_IRC_BASE                 0xf510
-#define TX4938_IRC_IRFLAG0              0xf510
-#define TX4938_IRC_IRFLAG1              0xf514
-#define TX4938_IRC_IRPOL                0xf518
-#define TX4938_IRC_IRRCNT               0xf51c
-#define TX4938_IRC_IRMASKINT            0xf520
-#define TX4938_IRC_IRMASKEXT            0xf524
-#define TX4938_IRC_IRDEN                0xf600
-#define TX4938_IRC_IRDM0                0xf604
-#define TX4938_IRC_IRDM1                0xf608
-#define TX4938_IRC_IRLVL0               0xf610
-#define TX4938_IRC_IRLVL1               0xf614
-#define TX4938_IRC_IRLVL2               0xf618
-#define TX4938_IRC_IRLVL3               0xf61c
-#define TX4938_IRC_IRLVL4               0xf620
-#define TX4938_IRC_IRLVL5               0xf624
-#define TX4938_IRC_IRLVL6               0xf628
-#define TX4938_IRC_IRLVL7               0xf62c
-#define TX4938_IRC_IRMSK                0xf640
-#define TX4938_IRC_IREDC                0xf660
-#define TX4938_IRC_IRPND                0xf680
-#define TX4938_IRC_IRCS                 0xf6a0
-#define TX4938_IRC_LIMIT                0xf6ff
-
-
 #ifndef __ASSEMBLY__
 
 #define tx4938_sdramcptr	((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 #define tx4938_dmaptr(ch)	((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 #define tx4938_ndfmcptr		((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
-#define tx4938_ircptr		((struct tx4938_irc_reg *)TX4938_IRC_REG)
 #define tx4938_pcicptr		((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
 #define tx4938_pcic1ptr		((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
 #define tx4938_ccfgptr		((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
new file mode 100644
index 00000000000..1c439e51b87
--- /dev/null
+++ b/include/asm-mips/txx9irq.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-mips/txx9irq.h
+ * TX39/TX49 interrupt controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9IRQ_H
+#define __ASM_TXX9IRQ_H
+
+#include <irq.h>
+
+#ifdef CONFIG_IRQ_CPU
+#define TXX9_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)
+#else
+#define TXX9_IRQ_BASE	0
+#endif
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXx9_MAX_IR 16
+#else
+#define TXx9_MAX_IR 32
+#endif
+
+void txx9_irq_init(unsigned long baseaddr);
+int txx9_irq(void);
+int txx9_irq_set_pri(int irc_irq, int new_pri);
+
+#endif /* __ASM_TXX9IRQ_H */
author	David Woodhouse <dwmw2@infradead.org>	2007-10-13 14:43:54 +0100
committer	David Woodhouse <dwmw2@infradead.org>	2007-10-13 14:43:54 +0100
commit	b160292cc216a50fd0cd386b0bda2cd48352c73b (patch)
tree	ef07cf98f91353ee4c9ec1e1ca7a2a5d9d4b538a /include/asm-mips
parent	b37bde147890c8fea8369a5a4e230dabdea4ebfb (diff)
parent	bbf25010f1a6b761914430f5fca081ec8c7accd1 (diff)