diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-15 19:04:58 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-15 19:04:58 -0700 |
| commit | 45158894d4d6704afbb4cefe55e5f6ca279fe12a (patch) | |
| tree | d57e745e2d0848d75cd4a46ca04178b16f186b50 /include/asm-powerpc/reg.h | |
| parent | 89a93f2f4834f8c126e8d9dd6b368d0b9e21ec3d (diff) | |
| parent | 84c3d4aaec3338201b449034beac41635866bddf (diff) | |
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (249 commits)
powerpc: Fix pte_update for CONFIG_PTE_64BIT and !PTE_ATOMIC_UPDATES
powerpc: Fix a build problem on ppc32 with new DMA_ATTRs
ibm_newemac: Add MII mode support to the EMAC RGMII bridge.
powerpc: Don't spin on sync instruction at boot time
powerpc: Add VSX load/store alignment exception handler
powerpc: fix giveup_vsx to save registers correctly
powerpc: support for latencytop
powerpc: Remove unnecessary condition when sanity-checking WIMG bits
powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT
powerpc: Add driver for Barrier Synchronization Register
powerpc: mman.h export fixups
powerpc/fsl: update crypto node definition and device tree instances
powerpc/fsl: Refactor device bindings
powerpc/85xx: Minor fixes for 85xxds and 8536ds board.
powerpc: Add 82xx/83xx/86xx to 6xx Multiplatform
powerpc/85xx: publish of device for cds platforms
powerpc/booke: don't reinitialize time base
powerpc/86xx: Refactor pic init
powerpc/CPM: Add i2c pins to dts and board setup
cpm_uart: Support uart_wait_until_sent()
...
Diffstat (limited to 'include/asm-powerpc/reg.h')
| -rw-r--r-- | include/asm-powerpc/reg.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index edc0cfd7f6e..bbccadfee0d 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -30,6 +30,7 @@ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ #define MSR_VEC_LG 25 /* Enable AltiVec */ +#define MSR_VSX_LG 23 /* Enable VSX */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ #define MSR_TGPR_LG 17 /* TLB Update registers in use */ @@ -71,6 +72,7 @@ #endif #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ +#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ @@ -240,7 +242,7 @@ #define HID0_DAPUEN (1<<8) /* Debug APU enable */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ -#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ #define HID0_ABE (1<<3) /* Address Broadcast Enable */ @@ -732,6 +734,8 @@ " .llong %1\n" \ " .llong 97b-98b\n" \ " .llong 99b-98b\n" \ + " .llong 0\n" \ + " .llong 0\n" \ ".previous" \ : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;}) #else |