diff options
author | David Woodhouse <David.Woodhouse@intel.com> | 2008-09-01 11:32:13 +0100 |
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committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-09-01 11:32:13 +0100 |
commit | 9d7548d4ca3c52ecb58f098a32b0756cdf8f96ee (patch) | |
tree | 651f7058bbaa2d8b2855286380d614afcf505118 /include/asm-x86/processor.h | |
parent | 31db6e9ea1dbdcf66b8227b4f7035dee1b1dd8c0 (diff) | |
parent | bef69ea0dcce574a425feb0a5aa4c63dd108b9a6 (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-x86/processor.h')
-rw-r--r-- | include/asm-x86/processor.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index 5f58da401b4..4df3e2f6fb5 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -728,6 +728,29 @@ extern unsigned long boot_option_idle_override; extern unsigned long idle_halt; extern unsigned long idle_nomwait; +/* + * on systems with caches, caches must be flashed as the absolute + * last instruction before going into a suspended halt. Otherwise, + * dirty data can linger in the cache and become stale on resume, + * leading to strange errors. + * + * perform a variety of operations to guarantee that the compiler + * will not reorder instructions. wbinvd itself is serializing + * so the processor will not reorder. + * + * Systems without cache can just go into halt. + */ +static inline void wbinvd_halt(void) +{ + mb(); + /* check for clflush to determine if wbinvd is legal */ + if (cpu_has_clflush) + asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); + else + while (1) + halt(); +} + extern void enable_sep_cpu(void); extern int sysenter_setup(void); |