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authorIngo Molnar <mingo@elte.hu>2009-09-20 20:24:58 +0200
committerIngo Molnar <mingo@elte.hu>2009-09-20 20:25:03 +0200
commitbfefb7a0c6e08736f2d5917c468467f134bf28bb (patch)
tree7aa7084114dc083fe5b4d7b532901bdeb67188e7 /include
parent8d0cc631f6dd0a9283ceb7d61d8b85ecbcd355ea (diff)
parent78f28b7c555359c67c2a0d23f7436e915329421e (diff)
Merge branch 'linus' into x86/urgent
Merge reason: Bring in changes that the next patch will depend on. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
-rw-r--r--include/linux/clocksource.h122
-rw-r--r--include/linux/cpufreq.h10
-rw-r--r--include/linux/delayacct.h1
-rw-r--r--include/linux/fuse.h29
-rw-r--r--include/linux/hrtimer.h2
-rw-r--r--include/linux/i2c/twl4030.h94
-rw-r--r--include/linux/jbd.h26
-rw-r--r--include/linux/jbd2.h2
-rw-r--r--include/linux/mfd/ab3100.h37
-rw-r--r--include/linux/mfd/core.h1
-rw-r--r--include/linux/mfd/ezx-pcap.h7
-rw-r--r--include/linux/mfd/mc13783-private.h396
-rw-r--r--include/linux/mfd/mc13783.h84
-rw-r--r--include/linux/mfd/pcf50633/adc.h3
-rw-r--r--include/linux/mfd/pcf50633/core.h1
-rw-r--r--include/linux/mfd/wm831x/auxadc.h216
-rw-r--r--include/linux/mfd/wm831x/core.h289
-rw-r--r--include/linux/mfd/wm831x/gpio.h55
-rw-r--r--include/linux/mfd/wm831x/irq.h764
-rw-r--r--include/linux/mfd/wm831x/otp.h162
-rw-r--r--include/linux/mfd/wm831x/pdata.h113
-rw-r--r--include/linux/mfd/wm831x/regulator.h1218
-rw-r--r--include/linux/mfd/wm831x/watchdog.h52
-rw-r--r--include/linux/mfd/wm8350/core.h7
-rw-r--r--include/linux/regulator/driver.h2
-rw-r--r--include/linux/sh_intc.h1
-rw-r--r--include/linux/taskstats_kern.h1
-rw-r--r--include/linux/time.h10
-rw-r--r--include/linux/timer.h5
-rw-r--r--include/linux/usb/m66592.h44
-rw-r--r--include/linux/usb/r8a66597.h375
-rw-r--r--include/trace/events/ext4.h142
-rw-r--r--include/trace/events/jbd2.h2
33 files changed, 4074 insertions, 199 deletions
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index 1219be4fb42..83d2fbd81b9 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -14,6 +14,7 @@
#include <linux/list.h>
#include <linux/cache.h>
#include <linux/timer.h>
+#include <linux/init.h>
#include <asm/div64.h>
#include <asm/io.h>
@@ -148,14 +149,11 @@ extern u64 timecounter_cyc2time(struct timecounter *tc,
* @disable: optional function to disable the clocksource
* @mask: bitmask for two's complement
* subtraction of non 64 bit counters
- * @mult: cycle to nanosecond multiplier (adjusted by NTP)
- * @mult_orig: cycle to nanosecond multiplier (unadjusted by NTP)
+ * @mult: cycle to nanosecond multiplier
* @shift: cycle to nanosecond divisor (power of two)
* @flags: flags describing special properties
* @vread: vsyscall based read
* @resume: resume function for the clocksource, if necessary
- * @cycle_interval: Used internally by timekeeping core, please ignore.
- * @xtime_interval: Used internally by timekeeping core, please ignore.
*/
struct clocksource {
/*
@@ -169,7 +167,6 @@ struct clocksource {
void (*disable)(struct clocksource *cs);
cycle_t mask;
u32 mult;
- u32 mult_orig;
u32 shift;
unsigned long flags;
cycle_t (*vread)(void);
@@ -181,19 +178,12 @@ struct clocksource {
#define CLKSRC_FSYS_MMIO_SET(mmio, addr) do { } while (0)
#endif
- /* timekeeping specific data, ignore */
- cycle_t cycle_interval;
- u64 xtime_interval;
- u32 raw_interval;
/*
* Second part is written at each timer interrupt
* Keep it in a different cache line to dirty no
* more than one cache line.
*/
cycle_t cycle_last ____cacheline_aligned_in_smp;
- u64 xtime_nsec;
- s64 error;
- struct timespec raw_time;
#ifdef CONFIG_CLOCKSOURCE_WATCHDOG
/* Watchdog related data, used by the framework */
@@ -202,8 +192,6 @@ struct clocksource {
#endif
};
-extern struct clocksource *clock; /* current clocksource */
-
/*
* Clock source flags bits::
*/
@@ -212,6 +200,7 @@ extern struct clocksource *clock; /* current clocksource */
#define CLOCK_SOURCE_WATCHDOG 0x10
#define CLOCK_SOURCE_VALID_FOR_HRES 0x20
+#define CLOCK_SOURCE_UNSTABLE 0x40
/* simplify initialization of mask field */
#define CLOCKSOURCE_MASK(bits) (cycle_t)((bits) < 64 ? ((1ULL<<(bits))-1) : -1)
@@ -268,108 +257,15 @@ static inline u32 clocksource_hz2mult(u32 hz, u32 shift_constant)
}
/**
- * clocksource_read: - Access the clocksource's current cycle value
- * @cs: pointer to clocksource being read
- *
- * Uses the clocksource to return the current cycle_t value
- */
-static inline cycle_t clocksource_read(struct clocksource *cs)
-{
- return cs->read(cs);
-}
-
-/**
- * clocksource_enable: - enable clocksource
- * @cs: pointer to clocksource
- *
- * Enables the specified clocksource. The clocksource callback
- * function should start up the hardware and setup mult and field
- * members of struct clocksource to reflect hardware capabilities.
- */
-static inline int clocksource_enable(struct clocksource *cs)
-{
- int ret = 0;
-
- if (cs->enable)
- ret = cs->enable(cs);
-
- /*
- * The frequency may have changed while the clocksource
- * was disabled. If so the code in ->enable() must update
- * the mult value to reflect the new frequency. Make sure
- * mult_orig follows this change.
- */
- cs->mult_orig = cs->mult;
-
- return ret;
-}
-
-/**
- * clocksource_disable: - disable clocksource
- * @cs: pointer to clocksource
- *
- * Disables the specified clocksource. The clocksource callback
- * function should power down the now unused hardware block to
- * save power.
- */
-static inline void clocksource_disable(struct clocksource *cs)
-{
- /*
- * Save mult_orig in mult so clocksource_enable() can
- * restore the value regardless if ->enable() updates
- * the value of mult or not.
- */
- cs->mult = cs->mult_orig;
-
- if (cs->disable)
- cs->disable(cs);
-}
-
-/**
- * cyc2ns - converts clocksource cycles to nanoseconds
- * @cs: Pointer to clocksource
- * @cycles: Cycles
+ * clocksource_cyc2ns - converts clocksource cycles to nanoseconds
*
- * Uses the clocksource and ntp ajdustment to convert cycle_ts to nanoseconds.
+ * Converts cycles to nanoseconds, using the given mult and shift.
*
* XXX - This could use some mult_lxl_ll() asm optimization
*/
-static inline s64 cyc2ns(struct clocksource *cs, cycle_t cycles)
-{
- u64 ret = (u64)cycles;
- ret = (ret * cs->mult) >> cs->shift;
- return ret;
-}
-
-/**
- * clocksource_calculate_interval - Calculates a clocksource interval struct
- *
- * @c: Pointer to clocksource.
- * @length_nsec: Desired interval length in nanoseconds.
- *
- * Calculates a fixed cycle/nsec interval for a given clocksource/adjustment
- * pair and interval request.
- *
- * Unless you're the timekeeping code, you should not be using this!
- */
-static inline void clocksource_calculate_interval(struct clocksource *c,
- unsigned long length_nsec)
+static inline s64 clocksource_cyc2ns(cycle_t cycles, u32 mult, u32 shift)
{
- u64 tmp;
-
- /* Do the ns -> cycle conversion first, using original mult */
- tmp = length_nsec;
- tmp <<= c->shift;
- tmp += c->mult_orig/2;
- do_div(tmp, c->mult_orig);
-
- c->cycle_interval = (cycle_t)tmp;
- if (c->cycle_interval == 0)
- c->cycle_interval = 1;
-
- /* Go back from cycles -> shifted ns, this time use ntp adjused mult */
- c->xtime_interval = (u64)c->cycle_interval * c->mult;
- c->raw_interval = ((u64)c->cycle_interval * c->mult_orig) >> c->shift;
+ return ((u64) cycles * mult) >> shift;
}
@@ -380,6 +276,8 @@ extern void clocksource_touch_watchdog(void);
extern struct clocksource* clocksource_get_next(void);
extern void clocksource_change_rating(struct clocksource *cs, int rating);
extern void clocksource_resume(void);
+extern struct clocksource * __init __weak clocksource_default_clock(void);
+extern void clocksource_mark_unstable(struct clocksource *cs);
#ifdef CONFIG_GENERIC_TIME_VSYSCALL
extern void update_vsyscall(struct timespec *ts, struct clocksource *c);
@@ -394,4 +292,6 @@ static inline void update_vsyscall_tz(void)
}
#endif
+extern void timekeeping_notify(struct clocksource *clock);
+
#endif /* _LINUX_CLOCKSOURCE_H */
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 161042746af..44717eb4763 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -65,6 +65,9 @@ static inline int cpufreq_unregister_notifier(struct notifier_block *nb,
struct cpufreq_governor;
+/* /sys/devices/system/cpu/cpufreq: entry point for global variables */
+extern struct kobject *cpufreq_global_kobject;
+
#define CPUFREQ_ETERNAL (-1)
struct cpufreq_cpuinfo {
unsigned int max_freq;
@@ -274,6 +277,13 @@ struct freq_attr {
ssize_t (*store)(struct cpufreq_policy *, const char *, size_t count);
};
+struct global_attr {
+ struct attribute attr;
+ ssize_t (*show)(struct kobject *kobj,
+ struct attribute *attr, char *buf);
+ ssize_t (*store)(struct kobject *a, struct attribute *b,
+ const char *c, size_t count);
+};
/*********************************************************************
* CPUFREQ 2.6. INTERFACE *
diff --git a/include/linux/delayacct.h b/include/linux/delayacct.h
index f352f06fa06..5076fe0c8a9 100644
--- a/include/linux/delayacct.h
+++ b/include/linux/delayacct.h
@@ -18,7 +18,6 @@
#define _LINUX_DELAYACCT_H
#include <linux/sched.h>
-#include <linux/taskstats_kern.h>
/*
* Per-task flags relevant to delay accounting
diff --git a/include/linux/fuse.h b/include/linux/fuse.h
index cf593bf9fd3..3e2925a34bf 100644
--- a/include/linux/fuse.h
+++ b/include/linux/fuse.h
@@ -30,6 +30,10 @@
* - add umask flag to input argument of open, mknod and mkdir
* - add notification messages for invalidation of inodes and
* directory entries
+ *
+ * 7.13
+ * - make max number of background requests and congestion threshold
+ * tunables
*/
#ifndef _LINUX_FUSE_H
@@ -37,11 +41,31 @@
#include <linux/types.h>
+/*
+ * Version negotiation:
+ *
+ * Both the kernel and userspace send the version they support in the
+ * INIT request and reply respectively.
+ *
+ * If the major versions match then both shall use the smallest
+ * of the two minor versions for communication.
+ *
+ * If the kernel supports a larger major version, then userspace shall
+ * reply with the major version it supports, ignore the rest of the
+ * INIT message and expect a new INIT message from the kernel with a
+ * matching major version.
+ *
+ * If the library supports a larger major version, then it shall fall
+ * back to the major protocol version sent by the kernel for
+ * communication and reply with that major version (and an arbitrary
+ * supported minor version).
+ */
+
/** Version number of this interface */
#define FUSE_KERNEL_VERSION 7
/** Minor version number of this interface */
-#define FUSE_KERNEL_MINOR_VERSION 12
+#define FUSE_KERNEL_MINOR_VERSION 13
/** The node ID of the root inode */
#define FUSE_ROOT_ID 1
@@ -427,7 +451,8 @@ struct fuse_init_out {
__u32 minor;
__u32 max_readahead;
__u32 flags;
- __u32 unused;
+ __u16 max_background;
+ __u16 congestion_threshold;
__u32 max_write;
};
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h
index 4759917adc7..ff037f0b1b4 100644
--- a/include/linux/hrtimer.h
+++ b/include/linux/hrtimer.h
@@ -91,7 +91,6 @@ enum hrtimer_restart {
* @function: timer expiry callback function
* @base: pointer to the timer base (per cpu and per clock)
* @state: state information (See bit values above)
- * @cb_entry: list head to enqueue an expired timer into the callback list
* @start_site: timer statistics field to store the site where the timer
* was started
* @start_comm: timer statistics field to store the name of the process which
@@ -108,7 +107,6 @@ struct hrtimer {
enum hrtimer_restart (*function)(struct hrtimer *);
struct hrtimer_clock_base *base;
unsigned long state;
- struct list_head cb_entry;
#ifdef CONFIG_TIMER_STATS
int start_pid;
void *start_site;
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl4030.h
index 3fd21d7cb6b..2d02dfd7076 100644
--- a/include/linux/i2c/twl4030.h
+++ b/include/linux/i2c/twl4030.h
@@ -223,19 +223,28 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
/* Power bus message definitions */
-#define DEV_GRP_NULL 0x0
-#define DEV_GRP_P1 0x1
-#define DEV_GRP_P2 0x2
-#define DEV_GRP_P3 0x4
+/* The TWL4030/5030 splits its power-management resources (the various
+ * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
+ * P3. These groups can then be configured to transition between sleep, wait-on
+ * and active states by sending messages to the power bus. See Section 5.4.2
+ * Power Resources of TWL4030 TRM
+ */
-#define RES_GRP_RES 0x0
-#define RES_GRP_PP 0x1
-#define RES_GRP_RC 0x2
+/* Processor groups */
+#define DEV_GRP_NULL 0x0
+#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
+#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
+#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
+
+/* Resource groups */
+#define RES_GRP_RES 0x0 /* Reserved */
+#define RES_GRP_PP 0x1 /* Power providers */
+#define RES_GRP_RC 0x2 /* Reset and control */
#define RES_GRP_PP_RC 0x3
-#define RES_GRP_PR 0x4
+#define RES_GRP_PR 0x4 /* Power references */
#define RES_GRP_PP_PR 0x5
#define RES_GRP_RC_PR 0x6
-#define RES_GRP_ALL 0x7
+#define RES_GRP_ALL 0x7 /* All resource groups */
#define RES_TYPE2_R0 0x0
@@ -246,6 +255,41 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
#define RES_STATE_SLEEP 0x8
#define RES_STATE_OFF 0x0
+/* Power resources */
+
+/* Power providers */
+#define RES_VAUX1 1
+#define RES_VAUX2 2
+#define RES_VAUX3 3
+#define RES_VAUX4 4
+#define RES_VMMC1 5
+#define RES_VMMC2 6
+#define RES_VPLL1 7
+#define RES_VPLL2 8
+#define RES_VSIM 9
+#define RES_VDAC 10
+#define RES_VINTANA1 11
+#define RES_VINTANA2 12
+#define RES_VINTDIG 13
+#define RES_VIO 14
+#define RES_VDD1 15
+#define RES_VDD2 16
+#define RES_VUSB_1V5 17
+#define RES_VUSB_1V8 18
+#define RES_VUSB_3V1 19
+#define RES_VUSBCP 20
+#define RES_REGEN 21
+/* Reset and control */
+#define RES_NRES_PWRON 22
+#define RES_CLKEN 23
+#define RES_SYSEN 24
+#define RES_HFCLKOUT 25
+#define RES_32KCLKOUT 26
+#define RES_RESET 27
+/* Power Reference */
+#define RES_Main_Ref 28
+
+#define TOTAL_RESOURCES 28
/*
* Power Bus Message Format ... these can be sent individually by Linux,
* but are usually part of downloaded scripts that are run when various
@@ -327,6 +371,36 @@ struct twl4030_usb_data {
enum twl4030_usb_mode usb_mode;
};
+struct twl4030_ins {
+ u16 pmb_message;
+ u8 delay;
+};
+
+struct twl4030_script {
+ struct twl4030_ins *script;
+ unsigned size;
+ u8 flags;
+#define TWL4030_WRST_SCRIPT (1<<0)
+#define TWL4030_WAKEUP12_SCRIPT (1<<1)
+#define TWL4030_WAKEUP3_SCRIPT (1<<2)
+#define TWL4030_SLEEP_SCRIPT (1<<3)
+};
+
+struct twl4030_resconfig {
+ u8 resource;
+ u8 devgroup; /* Processor group that Power resource belongs to */
+ u8 type; /* Power resource addressed, 6 / broadcast message */
+ u8 type2; /* Power resource addressed, 3 / broadcast message */
+};
+
+struct twl4030_power_data {
+ struct twl4030_script **scripts;
+ unsigned num;
+ struct twl4030_resconfig *resource_config;
+};
+
+extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
+
struct twl4030_platform_data {
unsigned irq_base, irq_end;
struct twl4030_bci_platform_data *bci;
@@ -334,6 +408,7 @@ struct twl4030_platform_data {
struct twl4030_madc_platform_data *madc;
struct twl4030_keypad_data *keypad;
struct twl4030_usb_data *usb;
+ struct twl4030_power_data *power;
/* LDO regulators */
struct regulator_init_data *vdac;
@@ -364,7 +439,6 @@ int twl4030_sih_setup(int module);
#define TWL4030_VAUX3_DEV_GRP 0x1F
#define TWL4030_VAUX3_DEDICATED 0x22
-
#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
extern int twl4030charger_usb_en(int enable);
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index c2049a04fa0..a1187a0c99b 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -446,7 +446,7 @@ struct transaction_s
/*
* Where in the log does this transaction's commit start? [no locking]
*/
- unsigned long t_log_start;
+ unsigned int t_log_start;
/* Number of buffers on the t_buffers list [j_list_lock] */
int t_nr_buffers;
@@ -701,26 +701,26 @@ struct journal_s
* Journal head: identifies the first unused block in the journal.
* [j_state_lock]
*/
- unsigned long j_head;
+ unsigned int j_head;
/*
* Journal tail: identifies the oldest still-used block in the journal.
* [j_state_lock]
*/
- unsigned long j_tail;
+ unsigned int j_tail;
/*
* Journal free: how many free blocks are there in the journal?
* [j_state_lock]
*/
- unsigned long j_free;
+ unsigned int j_free;
/*
* Journal start and end: the block numbers of the first usable block
* and one beyond the last usable block in the journal. [j_state_lock]
*/
- unsigned long j_first;
- unsigned long j_last;
+ unsigned int j_first;
+ unsigned int j_last;
/*
* Device, blocksize and starting block offset for the location where we
@@ -728,7 +728,7 @@ struct journal_s
*/
struct block_device *j_dev;
int j_blocksize;
- unsigned long j_blk_offset;
+ unsigned int j_blk_offset;
/*
* Device which holds the client fs. For internal journal this will be
@@ -859,7 +859,7 @@ extern void __journal_clean_data_list(transaction_t *transaction);
/* Log buffer allocation */
extern struct journal_head * journal_get_descriptor_buffer(journal_t *);
-int journal_next_log_block(journal_t *, unsigned long *);
+int journal_next_log_block(journal_t *, unsigned int *);
/* Commit management */
extern void journal_commit_transaction(journal_t *);
@@ -874,7 +874,7 @@ extern int
journal_write_metadata_buffer(transaction_t *transaction,
struct journal_head *jh_in,
struct journal_head **jh_out,
- unsigned long blocknr);
+ unsigned int blocknr);
/* Transaction locking */
extern void __wait_on_journal (journal_t *);
@@ -942,7 +942,7 @@ extern void journal_abort (journal_t *, int);
extern int journal_errno (journal_t *);
extern void journal_ack_err (journal_t *);
extern int journal_clear_err (journal_t *);
-extern int journal_bmap(journal_t *, unsigned long, unsigned long *);
+extern int journal_bmap(journal_t *, unsigned int, unsigned int *);
extern int journal_force_commit(journal_t *);
/*
@@ -976,14 +976,14 @@ extern int journal_init_revoke_caches(void);
extern void journal_destroy_revoke(journal_t *);
extern int journal_revoke (handle_t *,
- unsigned long, struct buffer_head *);
+ unsigned int, struct buffer_head *);
extern int journal_cancel_revoke(handle_t *, struct journal_head *);
extern void journal_write_revoke_records(journal_t *,
transaction_t *, int);
/* Recovery revoke support */
-extern int journal_set_revoke(journal_t *, unsigned long, tid_t);
-extern int journal_test_revoke(journal_t *, unsigned long, tid_t);
+extern int journal_set_revoke(journal_t *, unsigned int, tid_t);
+extern int journal_test_revoke(journal_t *, unsigned int, tid_t);
extern void journal_clear_revoke(journal_t *);
extern void journal_switch_revoke_table(journal_t *journal);
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index d97eb652d6c..52695d3dfd0 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -652,7 +652,7 @@ struct transaction_s
* This transaction is being forced and some process is
* waiting for it to finish.
*/
- int t_synchronous_commit:1;
+ unsigned int t_synchronous_commit:1;
/*
* For use by the filesystem to store fs-specific data
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h
index 7a3f316e384..e9aa4c9d749 100644
--- a/include/linux/mfd/ab3100.h
+++ b/include/linux/mfd/ab3100.h
@@ -6,6 +6,8 @@
*/
#include <linux/device.h>
+#include <linux/workqueue.h>
+#include <linux/regulator/machine.h>
#ifndef MFD_AB3100_H
#define MFD_AB3100_H
@@ -56,6 +58,14 @@
#define AB3100_STR_BATT_REMOVAL (0x40)
#define AB3100_STR_VBUS (0x80)
+/*
+ * AB3100 contains 8 regulators, one external regulator controller
+ * and a buck converter, further the LDO E and buck converter can
+ * have separate settings if they are in sleep mode, this is
+ * modeled as a separate regulator.
+ */
+#define AB3100_NUM_REGULATORS 10
+
/**
* struct ab3100
* @access_mutex: lock out concurrent accesses to the AB3100 registers
@@ -86,11 +96,30 @@ struct ab3100 {
bool startup_events_read;
};
-int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval);
-int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval);
-int ab3100_get_register_page(struct ab3100 *ab3100,
+/**
+ * struct ab3100_platform_data
+ * Data supplied to initialize board connections to the AB3100
+ * @reg_constraints: regulator constraints for target board
+ * the order of these constraints are: LDO A, C, D, E,
+ * F, G, H, K, EXT and BUCK.
+ * @reg_initvals: initial values for the regulator registers
+ * plus two sleep settings for LDO E and the BUCK converter.
+ * exactly AB3100_NUM_REGULATORS+2 values must be sent in.
+ * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
+ * BUCK sleep, LDO D. (LDO D need to be initialized last.)
+ * @external_voltage: voltage level of the external regulator.
+ */
+struct ab3100_platform_data {
+ struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
+ u8 reg_initvals[AB3100_NUM_REGULATORS+2];
+ int external_voltage;
+};
+
+int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
+int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
+int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
u8 first_reg, u8 *regvals, u8 numregs);
-int ab3100_mask_and_set_register(struct ab3100 *ab3100,
+int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
u8 reg, u8 andmask, u8 ormask);
u8 ab3100_get_chip_type(struct ab3100 *ab3100);
int ab3100_event_register(struct ab3100 *ab3100,
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index 49ef857cdb2..11d740b8831 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -23,6 +23,7 @@
*/
struct mfd_cell {
const char *name;
+ int id;
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index c12c3c0932b..e5124ceea76 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -25,9 +25,12 @@ struct pcap_chip;
int ezx_pcap_write(struct pcap_chip *, u8, u32);
int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
+int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
int pcap_to_irq(struct pcap_chip *, int);
+int irq_to_pcap(struct pcap_chip *, int);
int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
+void pcap_set_ts_bits(struct pcap_chip *, u32);
#define PCAP_SECOND_PORT 1
#define PCAP_CS_AH 2
@@ -224,7 +227,6 @@ int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
#define PCAP_LED1 1
#define PCAP_BL0 2
#define PCAP_BL1 3
-#define PCAP_VIB 4
#define PCAP_LED_3MA 0
#define PCAP_LED_4MA 1
#define PCAP_LED_5MA 2
@@ -243,9 +245,6 @@ int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
#define PCAP_LED0_C_SHIFT 15
#define PCAP_LED1_C_SHIFT 17
#define PCAP_BL1_SHIFT 20
-#define PCAP_VIB_MASK 0x3
-#define PCAP_VIB_SHIFT 20
-#define PCAP_VIB_EN (1 << 19)
/* RTC */
#define PCAP_RTC_DAY_MASK 0x3fff
diff --git a/include/linux/mfd/mc13783-private.h b/include/linux/mfd/mc13783-private.h
new file mode 100644
index 00000000000..47e698cb0f1
--- /dev/null
+++ b/include/linux/mfd/mc13783-private.h
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_MFD_MC13783_PRIV_H
+#define __LINUX_MFD_MC13783_PRIV_H
+
+#include <linux/platform_device.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/workqueue.h>
+#include <linux/mutex.h>
+
+struct mc13783_irq {
+ void (*handler)(int, void *);
+ void *data;
+};
+
+#define MC13783_NUM_IRQ 2
+#define MC13783_IRQ_TS 0
+#define MC13783_IRQ_REGULATOR 1
+
+#define MC13783_ADC_MODE_TS 1
+#define MC13783_ADC_MODE_SINGLE_CHAN 2
+#define MC13783_ADC_MODE_MULT_CHAN 3
+
+struct mc13783 {
+ int revision;
+ struct device *dev;
+ struct spi_device *spi_device;
+
+ int (*read_dev)(void *data, char reg, int count, u32 *dst);
+ int (*write_dev)(void *data, char reg, int count, const u32 *src);
+
+ struct mutex io_lock;
+ void *io_data;
+ int irq;
+ unsigned int flags;
+
+ struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
+ struct work_struct work;
+ struct completion adc_done;
+ unsigned int ts_active;
+ struct mutex adc_conv_lock;
+
+ struct mc13783_regulator_init_data *regulators;
+ int num_regulators;
+};
+
+int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
+int mc13783_reg_write(struct mc13783 *, int, u32);
+int mc13783_set_bits(struct mc13783 *, int, u32, u32);
+int mc13783_free_irq(struct mc13783 *mc13783, int irq);
+int mc13783_register_irq(struct mc13783 *mc13783, int irq,
+ void (*handler) (int, void *), void *data);
+
+#define MC13783_REG_INTERRUPT_STATUS_0 0
+#define MC13783_REG_INTERRUPT_MASK_0 1
+#define MC13783_REG_INTERRUPT_SENSE_0 2
+#define MC13783_REG_INTERRUPT_STATUS_1 3
+#define MC13783_REG_INTERRUPT_MASK_1 4
+#define MC13783_REG_INTERRUPT_SENSE_1 5
+#define MC13783_REG_POWER_UP_MODE_SENSE 6
+#define MC13783_REG_REVISION 7
+#define MC13783_REG_SEMAPHORE 8
+#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
+#define MC13783_REG_ARBITRATION_SWITCHERS 10
+#define MC13783_REG_ARBITRATION_REGULATORS_0 11
+#define MC13783_REG_ARBITRATION_REGULATORS_1 12
+#define MC13783_REG_POWER_CONTROL_0 13
+#define MC13783_REG_POWER_CONTROL_1 14
+#define MC13783_REG_POWER_CONTROL_2 15
+#define MC13783_REG_REGEN_ASSIGNMENT 16
+#define MC13783_REG_CONTROL_SPARE 17
+#define MC13783_REG_MEMORY_A 18
+#define MC13783_REG_MEMORY_B 19
+#define MC13783_REG_RTC_TIME 20
+#define MC13783_REG_RTC_ALARM 21
+#define MC13783_REG_RTC_DAY 22
+#define MC13783_REG_RTC_DAY_ALARM 23
+#define MC13783_REG_SWITCHERS_0 24
+#define MC13783_REG_SWITCHERS_1 25
+#define MC13783_REG_SWITCHERS_2 26
+#define MC13783_REG_SWITCHERS_3 27
+#define MC13783_REG_SWITCHERS_4 28
+#define MC13783_REG_SWITCHERS_5 29
+#define MC13783_REG_REGULATOR_SETTING_0 30
+#define MC13783_REG_REGULATOR_SETTING_1 31
+#define MC13783_REG_REGULATOR_MODE_0 32
+#define MC13783_REG_REGULATOR_MODE_1 33
+#define MC13783_REG_POWER_MISCELLANEOUS 34
+#define MC13783_REG_POWER_SPARE 35
+#define MC13783_REG_AUDIO_RX_0 36
+#define MC13783_REG_AUDIO_RX_1 37
+#define MC13783_REG_AUDIO_TX 38
+#define MC13783_REG_AUDIO_SSI_NETWORK 39
+#define MC13783_REG_AUDIO_CODEC 40
+#define MC13783_REG_AUDIO_STEREO_DAC 41
+#define MC13783_REG_AUDIO_SPARE 42
+#define MC13783_REG_ADC_0 43
+#define MC13783_REG_ADC_1 44
+#define MC13783_REG_ADC_2 45
+#define MC13783_REG_ADC_3 46
+#define MC13783_REG_ADC_4 47
+#define MC13783_REG_CHARGER 48
+#define MC13783_REG_USB 49
+#define MC13783_REG_CHARGE_USB_SPARE 50
+#define MC13783_REG_LED_CONTROL_0 51
+#define MC13783_REG_LED_CONTROL_1 52
+#define MC13783_REG_LED_CONTROL_2 53
+#define MC13783_REG_LED_CONTROL_3 54
+#define MC13783_REG_LED_CONTROL_4 55
+#define MC13783_REG_LED_CONTROL_5 56
+#define MC13783_REG_SPARE 57
+#define MC13783_REG_TRIM_0 58
+#define MC13783_REG_TRIM_1 59
+#define MC13783_REG_TEST_0 60
+#define MC13783_REG_TEST_1 61
+#define MC13783_REG_TEST_2 62
+#define MC13783_REG_TEST_3 63
+#define MC13783_REG_NB 64
+
+
+/*
+ * Interrupt Status
+ */
+#define MC13783_INT_STAT_ADCDONEI (1 << 0)
+#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
+#define MC13783_INT_STAT_TSI (1 << 2)
+#define MC13783_INT_STAT_WHIGHI (1 << 3)
+#define MC13783_INT_STAT_WLOWI (1 << 4)
+#define MC13783_INT_STAT_CHGDETI (1 << 6)
+#define MC13783_INT_STAT_CHGOVI (1 << 7)
+#define MC13783_INT_STAT_CHGREVI (1 << 8)
+#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
+#define MC13783_INT_STAT_CCCVI (1 << 10)
+#define MC13783_INT_STAT_CHGCURRI (1 << 11)
+#define MC13783_INT_STAT_BPONI (1 << 12)
+#define MC13783_INT_STAT_LOBATLI (1 << 13)
+#define MC13783_INT_STAT_LOBATHI (1 << 14)
+#define MC13783_INT_STAT_UDPI (1 << 15)
+#define MC13783_INT_STAT_USBI (1 << 16)
+#define MC13783_INT_STAT_IDI (1 << 19)
+#define MC13783_INT_STAT_Unused (1 << 20)
+#define MC13783_INT_STAT_SE1I (1 << 21)
+#define MC13783_INT_STAT_CKDETI (1 << 22)
+#define MC13783_INT_STAT_UDMI (1 << 23)
+
+/*
+ * Interrupt Mask
+ */
+#define MC13783_INT_MASK_ADCDONEM (1 << 0)
+#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
+#define MC13783_INT_MASK_TSM (1 << 2)
+#define MC13783_INT_MASK_WHIGHM (1 << 3)
+#define MC13783_INT_MASK_WLOWM (1 << 4)
+#define MC13783_INT_MASK_CHGDETM (1 << 6)
+#define MC13783_INT_MASK_CHGOVM (1 << 7)
+#define MC13783_INT_MASK_CHGREVM (1 << 8)
+#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
+#define MC13783_INT_MASK_CCCVM (1 << 10)
+#define MC13783_INT_MASK_CHGCURRM (1 << 11)
+#define MC13783_INT_MASK_BPONM (1 << 12)
+#define MC13783_INT_MASK_LOBATLM (1 << 13)
+#define MC13783_INT_MASK_LOBATHM (1 << 14)
+#define MC13783_INT_MASK_UDPM (1 << 15)
+#define MC13783_INT_MASK_USBM (1 << 16)
+#define MC13783_INT_MASK_IDM (1 << 19)
+#define MC13783_INT_MASK_SE1M (1 << 21)
+#define MC13783_INT_MASK_CKDETM (1 << 22)
+
+/*
+ * Reg Regulator Mode 0
+ */
+#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
+#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
+#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
+#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
+#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
+#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
+#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
+#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
+#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
+#define MC13783_REGCTRL_VDIG_EN (1 << 9)
+#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
+#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
+#define MC13783_REGCTRL_VGEN_EN (1 << 12)
+#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
+#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
+#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
+#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
+#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
+#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
+#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
+#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
+#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
+#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
+#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
+
+/*
+ * Reg Regulator Mode 1
+ */
+#define MC13783_REGCTRL_VSIM_EN (1 << 0)
+#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
+#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
+#define MC13783_REGCTRL_VESIM_EN (1 << 3)
+#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
+#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
+#define MC13783_REGCTRL_VCAM_EN (1 << 6)
+#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
+#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
+#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
+#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
+#define MC13783_REGCTRL_VVIB_EN (1 << 11)
+#define MC13783_REGCTRL_VRF1_EN (1 << 12)
+#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
+#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
+#define MC13783_REGCTRL_VRF2_EN (1 << 15)
+#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
+#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
+#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
+#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
+#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
+#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
+#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
+#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
+
+/*
+ * Reg Regulator Misc.
+ */
+#define MC13783_REGCTRL_GPO1_EN (1 << 6)
+#define MC13783_REGCTRL_GPO2_EN (1 << 8)
+#define MC13783_REGCTRL_GPO3_EN (1 << 10)
+#define MC13783_REGCTRL_GPO4_EN (1 << 12)
+#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
+
+/*
+ * Reg Switcher 4
+ */
+#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
+#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
+#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
+#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
+#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
+#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
+#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
+#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
+#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
+#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
+#define MC13783_SWCTRL_PLL_EN (1 << 18)
+#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
+
+/*
+ * Reg Switcher 5
+ */
+#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
+#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
+#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
+#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
+#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
+#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
+#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
+#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
+#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
+#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
+#define MC13783_SWSET_SW3 (1 << 18)
+#define MC13783_SWCTRL_SW3_EN (1 << 20)
+#define MC13783_SWCTRL_SW3_STBY (1 << 21)
+#define MC13783_SWCTRL_SW3_MODE (1 << 22)
+
+/*
+ * ADC/Touch
+ */
+#define MC13783_ADC0_LICELLCON (1 << 0)
+#define MC13783_ADC0_CHRGICON (1 << 1)
+#define MC13783_ADC0_BATICON (1 << 2)
+#define MC13783_ADC0_RTHEN (1 << 3)
+#define MC13783_ADC0_DTHEN (1 << 4)
+#define MC13783_ADC0_UIDEN (1 << 5)
+#define MC13783_ADC0_ADOUTEN (1 << 6)
+#define MC13783_ADC0_ADOUTPER (1 << 7)
+#define MC13783_ADC0_ADREFEN (1 << 10)
+#define MC13783_ADC0_ADREFMODE (1 << 11)
+#define MC13783_ADC0_TSMOD0 (1 << 12)
+#define MC13783_ADC0_TSMOD1 (1 << 13)
+#define MC13783_ADC0_TSMOD2 (1 << 14)
+#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
+#define MC13783_ADC0_ADINC1 (1 << 16)
+#define MC13783_ADC0_ADINC2 (1 << 17)
+#define MC13783_ADC0_WCOMP (1 << 18)
+#define MC13783_ADC0_ADCBIS0 (1 << 23)
+
+#define MC13783_ADC1_ADEN (1 << 0)
+#define MC13783_ADC1_RAND (1 << 1)
+#define MC13783_ADC1_ADSEL (1 << 3)
+#define MC13783_ADC1_TRIGMASK (1 << 4)
+#define MC13783_ADC1_ADA10 (1 << 5)
+#define MC13783_ADC1_ADA11 (1 << 6)
+#define MC13783_ADC1_ADA12 (1 << 7)
+#define MC13783_ADC1_ADA20 (1 << 8)
+#define MC13783_ADC1_ADA21 (1 << 9)
+#define MC13783_ADC1_ADA22 (1 << 10)
+#define MC13783_ADC1_ATO0 (1 << 11)
+#define MC13783_ADC1_ATO1 (1 << 12)
+#define MC13783_ADC1_ATO2 (1 << 13)
+#define MC13783_ADC1_ATO3 (1 << 14)
+#define MC13783_ADC1_ATO4 (1 << 15)
+#define MC13783_ADC1_ATO5 (1 << 16)
+#define MC13783_ADC1_ATO6 (1 << 17)
+#define MC13783_ADC1_ATO7 (1 << 18)
+#define MC13783_ADC1_ATOX (1 << 19)
+#define MC13783_ADC1_ASC (1 << 20)
+#define MC13783_ADC1_ADTRIGIGN (1 << 21)
+#define MC13783_ADC1_ADONESHOT (1 << 22)
+#define MC13783_ADC1_ADCBIS1 (1 << 23)
+
+#define MC13783_ADC1_CHAN0_SHIFT 5
+#define MC13783_ADC1_CHAN1_SHIFT 8
+
+#define MC13783_ADC2_ADD10 (1 << 2)
+#define MC13783_ADC2_ADD11 (1 << 3)
+#define MC13783_ADC2_ADD12 (1 << 4)
+#define MC13783_ADC2_ADD13 (1 << 5)
+#define MC13783_ADC2_ADD14 (1 << 6)
+#define MC13783_ADC2_ADD15 (1 << 7)
+#define MC13783_ADC2_ADD16 (1 << 8)
+#define MC13783_ADC2_ADD17 (1 << 9)
+#define MC13783_ADC2_ADD18 (1 << 10)
+#define MC13783_ADC2_ADD19 (1 << 11)
+#define MC13783_ADC2_ADD20 (1 << 14)
+#define MC13783_ADC2_ADD21 (1 << 15)
+#define MC13783_ADC2_ADD22 (1 << 16)
+#define MC13783_ADC2_ADD23 (1 << 17)
+#define MC13783_ADC2_ADD24 (1 << 18)
+#define MC13783_ADC2_ADD25 (1 << 19)
+#define MC13783_ADC2_ADD26 (1 << 20)
+#define MC13783_ADC2_ADD27 (1 << 21)
+#define MC13783_ADC2_ADD28 (1 << 22)
+#define MC13783_ADC2_ADD29 (1 << 23)
+
+#define MC13783_ADC3_WHIGH0 (1 << 0)
+#define MC13783_ADC3_WHIGH1 (1 << 1)
+#define MC13783_ADC3_WHIGH2 (1 << 2)
+#define MC13783_ADC3_WHIGH3 (1 << 3)
+#define MC13783_ADC3_WHIGH4 (1 << 4)
+#define MC13783_ADC3_WHIGH5 (1 << 5)
+#define MC13783_ADC3_ICID0 (1 << 6)
+#define MC13783_ADC3_ICID1 (1 << 7)
+#define MC13783_ADC3_ICID2 (1 << 8)
+#define MC13783_ADC3_WLOW0 (1 << 9)
+#define MC13783_ADC3_WLOW1 (1 << 10)
+#define MC13783_ADC3_WLOW2 (1 << 11)
+#define MC13783_ADC3_WLOW3 (1 << 12)
+#define MC13783_ADC3_WLOW4 (1 << 13)
+#define MC13783_ADC3_WLOW5 (1 << 14)
+#define MC13783_ADC3_ADCBIS2 (1 << 23)
+
+#define MC13783_ADC4_ADDBIS10 (1 << 2)
+#define MC13783_ADC4_ADDBIS11 (1 << 3)
+#define MC13783_ADC4_ADDBIS12 (1 << 4)
+#define MC13783_ADC4_ADDBIS13 (1 << 5)
+#define MC13783_ADC4_ADDBIS14 (1 << 6)
+#define MC13783_ADC4_ADDBIS15 (1 << 7)
+#define MC13783_ADC4_ADDBIS16 (1 << 8)
+#define MC13783_ADC4_ADDBIS17 (1 << 9)
+#define MC13783_ADC4_ADDBIS18 (1 << 10)
+#define MC13783_ADC4_ADDBIS19 (1 << 11)
+#define MC13783_ADC4_ADDBIS20 (1 << 14)
+#define MC13783_ADC4_ADDBIS21 (1 << 15)
+#define MC13783_ADC4_ADDBIS22 (1 << 16)
+#define MC13783_ADC4_ADDBIS23 (1 << 17)
+#define MC13783_ADC4_ADDBIS24 (1 << 18)
+#define MC13783_ADC4_ADDBIS25 (1 << 19)
+#define MC13783_ADC4_ADDBIS26 (1 << 20)
+#define MC13783_ADC4_ADDBIS27 (1 << 21)
+#define MC13783_ADC4_ADDBIS28 (1 << 22)
+#define MC13783_ADC4_ADDBIS29 (1 << 23)
+
+#endif /* __LINUX_MFD_MC13783_PRIV_H */
+
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
new file mode 100644
index 00000000000..b3a2a724357
--- /dev/null
+++ b/include/linux/mfd/mc13783.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __INCLUDE_LINUX_MFD_MC13783_H
+#define __INCLUDE_LINUX_MFD_MC13783_H
+
+struct mc13783;
+struct regulator_init_data;
+
+struct mc13783_regulator_init_data {
+ int id;
+ struct regulator_init_data *init_data;
+};
+
+struct mc13783_platform_data {
+ struct mc13783_regulator_init_data *regulators;
+ int num_regulators;
+ unsigned int flags;
+};
+
+/* mc13783_platform_data flags */
+#define MC13783_USE_TOUCHSCREEN (1 << 0)
+#define MC13783_USE_CODEC (1 << 1)
+#define MC13783_USE_ADC (1 << 2)
+#define MC13783_USE_RTC (1 << 3)
+#define MC13783_USE_REGULATOR (1 << 4)
+
+int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
+ unsigned int channel, unsigned int *sample);
+
+void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
+
+#define MC13783_SW_SW1A 0
+#define MC13783_SW_SW1B 1
+#define MC13783_SW_SW2A 2
+#define MC13783_SW_SW2B 3
+#define MC13783_SW_SW3 4
+#define MC13783_SW_PLL 5
+#define MC13783_REGU_VAUDIO 6
+#define MC13783_REGU_VIOHI 7
+#define MC13783_REGU_VIOLO 8
+#define MC13783_REGU_VDIG 9
+#define MC13783_REGU_VGEN 10
+#define MC13783_REGU_VRFDIG 11
+#define MC13783_REGU_VRFREF 12
+#define MC13783_REGU_VRFCP 13
+#define MC13783_REGU_VSIM 14
+#define MC13783_REGU_VESIM 15
+#define MC13783_REGU_VCAM 16
+#define MC13783_REGU_VRFBG 17
+#define MC13783_REGU_VVIB 18
+#define MC13783_REGU_VRF1 19
+#define MC13783_REGU_VRF2 20
+#define MC13783_REGU_VMMC1 21
+#define MC13783_REGU_VMMC2 22
+#define MC13783_REGU_GPO1 23
+#define MC13783_REGU_GPO2 24
+#define MC13783_REGU_GPO3 25
+#define MC13783_REGU_GPO4 26
+#define MC13783_REGU_V1 27
+#define MC13783_REGU_V2 28
+#define MC13783_REGU_V3 29
+#define MC13783_REGU_V4 30
+
+#endif /* __INCLUDE_LINUX_MFD_MC13783_H */
+
diff --git a/include/linux/mfd/pcf50633/adc.h b/include/linux/mfd/pcf50633/adc.h
index 56669b4183a..b35e62801ff 100644
--- a/include/linux/mfd/pcf50633/adc.h
+++ b/include/linux/mfd/pcf50633/adc.h
@@ -25,7 +25,8 @@
#define PCF50633_REG_ADCS3 0x57
#define PCF50633_ADCC1_ADCSTART 0x01
-#define PCF50633_ADCC1_RES_10BIT 0x02
+#define PCF50633_ADCC1_RES_8BIT 0x02
+#define PCF50633_ADCC1_RES_10BIT 0x00
#define PCF50633_ADCC1_AVERAGE_NO 0x00
#define PCF50633_ADCC1_AVERAGE_4 0x04
#define PCF50633_ADCC1_AVERAGE_8 0x08
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index c8f51c3c0a7..9aba7b779fb 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -136,6 +136,7 @@ struct pcf50633 {
int irq;
struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
struct work_struct irq_work;
+ struct workqueue_struct *work_queue;
struct mutex lock;
u8 mask_regs[5];
diff --git a/include/linux/mfd/wm831x/auxadc.h b/include/linux/mfd/wm831x/auxadc.h
new file mode 100644
index 00000000000..b132067e9e9
--- /dev/null
+++ b/include/linux/mfd/wm831x/auxadc.h
@@ -0,0 +1,216 @@
+/*
+ * include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_AUXADC_H__
+#define __MFD_WM831X_AUXADC_H__
+
+/*
+ * R16429 (0x402D) - AuxADC Data
+ */
+#define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
+#define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */
+#define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */
+#define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
+#define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
+#define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
+
+/*
+ * R16430 (0x402E) - AuxADC Control
+ */
+#define WM831X_AUX_ENA 0x8000 /* AUX_ENA */
+#define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */
+#define WM831X_AUX_ENA_SHIFT 15 /* AUX_ENA */
+#define WM831X_AUX_ENA_WIDTH 1 /* AUX_ENA */
+#define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */
+#define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */
+#define WM831X_AUX_CVT_ENA_SHIFT 14 /* AUX_CVT_ENA */
+#define WM831X_AUX_CVT_ENA_WIDTH 1 /* AUX_CVT_ENA */
+#define WM831X_AUX_SLPENA 0x1000 /* AUX_SLPENA */
+#define WM831X_AUX_SLPENA_MASK 0x1000 /* AUX_SLPENA */
+#define WM831X_AUX_SLPENA_SHIFT 12 /* AUX_SLPENA */
+#define WM831X_AUX_SLPENA_WIDTH 1 /* AUX_SLPENA */
+#define WM831X_AUX_FRC_ENA 0x0800 /* AUX_FRC_ENA */
+#define WM831X_AUX_FRC_ENA_MASK 0x0800 /* AUX_FRC_ENA */
+#define WM831X_AUX_FRC_ENA_SHIFT 11 /* AUX_FRC_ENA */
+#define WM831X_AUX_FRC_ENA_WIDTH 1 /* AUX_FRC_ENA */
+#define WM831X_AUX_RATE_MASK 0x003F /* AUX_RATE - [5:0] */
+#define WM831X_AUX_RATE_SHIFT 0 /* AUX_RATE - [5:0] */
+#define WM831X_AUX_RATE_WIDTH 6 /* AUX_RATE - [5:0] */
+
+/*
+ * R16431 (0x402F) - AuxADC Source
+ */
+#define WM831X_AUX_CAL_SEL 0x8000 /* AUX_CAL_SEL */
+#define WM831X_AUX_CAL_SEL_MASK 0x8000 /* AUX_CAL_SEL */
+#define WM831X_AUX_CAL_SEL_SHIFT 15 /* AUX_CAL_SEL */
+#define WM831X_AUX_CAL_SEL_WIDTH 1 /* AUX_CAL_SEL */
+#define WM831X_AUX_BKUP_BATT_SEL 0x0400 /* AUX_BKUP_BATT_SEL */
+#define WM831X_AUX_BKUP_BATT_SEL_MASK 0x0400 /* AUX_BKUP_BATT_SEL */
+#define WM831X_AUX_BKUP_BATT_SEL_SHIFT 10 /* AUX_BKUP_BATT_SEL */
+#define WM831X_AUX_BKUP_BATT_SEL_WIDTH 1 /* AUX_BKUP_BATT_SEL */
+#define WM831X_AUX_WALL_SEL 0x0200 /* AUX_WALL_SEL */
+#define WM831X_AUX_WALL_SEL_MASK 0x0200 /* AUX_WALL_SEL */
+#define WM831X_AUX_WALL_SEL_SHIFT 9 /* AUX_WALL_SEL */
+#define WM831X_AUX_WALL_SEL_WIDTH 1 /* AUX_WALL_SEL */
+#define WM831X_AUX_BATT_SEL 0x0100 /* AUX_BATT_SEL */
+#define WM831X_AUX_BATT_SEL_MASK 0x0100 /* AUX_BATT_SEL */
+#define WM831X_AUX_BATT_SEL_SHIFT 8 /* AUX_BATT_SEL */
+#define WM831X_AUX_BATT_SEL_WIDTH 1 /* AUX_BATT_SEL */
+#define WM831X_AUX_USB_SEL 0x0080 /* AUX_USB_SEL */
+#define WM831X_AUX_USB_SEL_MASK 0x0080 /* AUX_USB_SEL */
+#define WM831X_AUX_USB_SEL_SHIFT 7 /* AUX_USB_SEL */
+#define WM831X_AUX_USB_SEL_WIDTH 1 /* AUX_USB_SEL */
+#define WM831X_AUX_SYSVDD_SEL 0x0040 /* AUX_SYSVDD_SEL */
+#define WM831X_AUX_SYSVDD_SEL_MASK 0x0040 /* AUX_SYSVDD_SEL */
+#define WM831X_AUX_SYSVDD_SEL_SHIFT 6 /* AUX_SYSVDD_SEL */
+#define WM831X_AUX_SYSVDD_SEL_WIDTH 1 /* AUX_SYSVDD_SEL */
+#define WM831X_AUX_BATT_TEMP_SEL 0x0020 /* AUX_BATT_TEMP_SEL */
+#define WM831X_AUX_BATT_TEMP_SEL_MASK 0x0020 /* AUX_BATT_TEMP_SEL */
+#define WM831X_AUX_BATT_TEMP_SEL_SHIFT 5 /* AUX_BATT_TEMP_SEL */
+#define WM831X_AUX_BATT_TEMP_SEL_WIDTH 1 /* AUX_BATT_TEMP_SEL */
+#define WM831X_AUX_CHIP_TEMP_SEL 0x0010 /* AUX_CHIP_TEMP_SEL */
+#define WM831X_AUX_CHIP_TEMP_SEL_MASK 0x0010 /* AUX_CHIP_TEMP_SEL */
+#define WM831X_AUX_CHIP_TEMP_SEL_SHIFT 4 /* AUX_CHIP_TEMP_SEL */
+#define WM831X_AUX_CHIP_TEMP_SEL_WIDTH 1 /* AUX_CHIP_TEMP_SEL */
+#define WM831X_AUX_AUX4_SEL 0x0008 /* AUX_AUX4_SEL */
+#define WM831X_AUX_AUX4_SEL_MASK 0x0008 /* AUX_AUX4_SEL */
+#define WM831X_AUX_AUX4_SEL_SHIFT 3 /* AUX_AUX4_SEL */
+#define WM831X_AUX_AUX4_SEL_WIDTH 1 /* AUX_AUX4_SEL */
+#define WM831X_AUX_AUX3_SEL 0x0004 /* AUX_AUX3_SEL */
+#define WM831X_AUX_AUX3_SEL_MASK 0x0004 /* AUX_AUX3_SEL */
+#define WM831X_AUX_AUX3_SEL_SHIFT 2 /* AUX_AUX3_SEL */
+#define WM831X_AUX_AUX3_SEL_WIDTH 1 /* AUX_AUX3_SEL */
+#define WM831X_AUX_AUX2_SEL 0x0002 /* AUX_AUX2_SEL */
+#define WM831X_AUX_AUX2_SEL_MASK 0x0002 /* AUX_AUX2_SEL */
+#define WM831X_AUX_AUX2_SEL_SHIFT 1 /* AUX_AUX2_SEL */
+#define WM831X_AUX_AUX2_SEL_WIDTH 1 /* AUX_AUX2_SEL */
+#define WM831X_AUX_AUX1_SEL 0x0001 /* AUX_AUX1_SEL */
+#define WM831X_AUX_AUX1_SEL_MASK 0x0001 /* AUX_AUX1_SEL */
+#define WM831X_AUX_AUX1_SEL_SHIFT 0 /* AUX_AUX1_SEL */
+#define WM831X_AUX_AUX1_SEL_WIDTH 1 /* AUX_AUX1_SEL */
+
+/*
+ * R16432 (0x4030) - Comparator Control
+ */
+#define WM831X_DCOMP4_STS 0x0800 /* DCOMP4_STS */
+#define WM831X_DCOMP4_STS_MASK 0x0800 /* DCOMP4_STS */
+#define WM831X_DCOMP4_STS_SHIFT 11 /* DCOMP4_STS */
+#define WM831X_DCOMP4_STS_WIDTH 1 /* DCOMP4_STS */
+#define WM831X_DCOMP3_STS 0x0400 /* DCOMP3_STS */
+#define WM831X_DCOMP3_STS_MASK 0x0400 /* DCOMP3_STS */
+#define WM831X_DCOMP3_STS_SHIFT 10 /* DCOMP3_STS */
+#define WM831X_DCOMP3_STS_WIDTH 1 /* DCOMP3_STS */
+#define WM831X_DCOMP2_STS 0x0200 /* DCOMP2_STS */
+#define WM831X_DCOMP2_STS_MASK 0x0200 /* DCOMP2_STS */
+#define WM831X_DCOMP2_STS_SHIFT 9 /* DCOMP2_STS */
+#define WM831X_DCOMP2_STS_WIDTH 1 /* DCOMP2_STS */
+#define WM831X_DCOMP1_STS 0x0100 /* DCOMP1_STS */
+#define WM831X_DCOMP1_STS_MASK 0x0100 /* DCOMP1_STS */
+#define WM831X_DCOMP1_STS_SHIFT 8 /* DCOMP1_STS */
+#define WM831X_DCOMP1_STS_WIDTH 1 /* DCOMP1_STS */
+#define WM831X_DCMP4_ENA 0x0008 /* DCMP4_ENA */
+#define WM831X_DCMP4_ENA_MASK 0x0008 /* DCMP4_ENA */
+#define WM831X_DCMP4_ENA_SHIFT 3 /* DCMP4_ENA */
+#define WM831X_DCMP4_ENA_WIDTH 1 /* DCMP4_ENA */
+#define WM831X_DCMP3_ENA 0x0004 /* DCMP3_ENA */
+#define WM831X_DCMP3_ENA_MASK 0x0004 /* DCMP3_ENA */
+#define WM831X_DCMP3_ENA_SHIFT 2 /* DCMP3_ENA */
+#define WM831X_DCMP3_ENA_WIDTH 1 /* DCMP3_ENA */
+#define WM831X_DCMP2_ENA 0x0002 /* DCMP2_ENA */
+#define WM831X_DCMP2_ENA_MASK 0x0002 /* DCMP2_ENA */
+#define WM831X_DCMP2_ENA_SHIFT 1 /* DCMP2_ENA */
+#define WM831X_DCMP2_ENA_WIDTH 1 /* DCMP2_ENA */
+#define WM831X_DCMP1_ENA 0x0001 /* DCMP1_ENA */
+#define WM831X_DCMP1_ENA_MASK 0x0001 /* DCMP1_ENA */
+#define WM831X_DCMP1_ENA_SHIFT 0 /* DCMP1_ENA */
+#define WM831X_DCMP1_ENA_WIDTH 1 /* DCMP1_ENA */
+
+/*
+ * R16433 (0x4031) - Comparator 1
+ */
+#define WM831X_DCMP1_SRC_MASK 0xE000 /* DCMP1_SRC - [15:13] */
+#define WM831X_DCMP1_SRC_SHIFT 13 /* DCMP1_SRC - [15:13] */
+#define WM831X_DCMP1_SRC_WIDTH 3 /* DCMP1_SRC - [15:13] */
+#define WM831X_DCMP1_GT 0x1000 /* DCMP1_GT */
+#define WM831X_DCMP1_GT_MASK 0x1000 /* DCMP1_GT */
+#define WM831X_DCMP1_GT_SHIFT 12 /* DCMP1_GT */
+#define WM831X_DCMP1_GT_WIDTH 1 /* DCMP1_GT */
+#define WM831X_DCMP1_THR_MASK 0x0FFF /* DCMP1_THR - [11:0] */
+#define WM831X_DCMP1_THR_SHIFT 0 /* DCMP1_THR - [11:0] */
+#define WM831X_DCMP1_THR_WIDTH 12 /* DCMP1_THR - [11:0] */
+
+/*
+ * R16434 (0x4032) - Comparator 2
+ */
+#define WM831X_DCMP2_SRC_MASK 0xE000 /* DCMP2_SRC - [15:13] */
+#define WM831X_DCMP2_SRC_SHIFT 13 /* DCMP2_SRC - [15:13] */
+#define WM831X_DCMP2_SRC_WIDTH 3 /* DCMP2_SRC - [15:13] */
+#define WM831X_DCMP2_GT 0x1000 /* DCMP2_GT */
+#define WM831X_DCMP2_GT_MASK 0x1000 /* DCMP2_GT */
+#define WM831X_DCMP2_GT_SHIFT 12 /* DCMP2_GT */
+#define WM831X_DCMP2_GT_WIDTH 1 /* DCMP2_GT */
+#define WM831X_DCMP2_THR_MASK 0x0FFF /* DCMP2_THR - [11:0] */
+#define WM831X_DCMP2_THR_SHIFT 0 /* DCMP2_THR - [11:0] */
+#define WM831X_DCMP2_THR_WIDTH 12 /* DCMP2_THR - [11:0] */
+
+/*
+ * R16435 (0x4033) - Comparator 3
+ */
+#define WM831X_DCMP3_SRC_MASK 0xE000 /* DCMP3_SRC - [15:13] */
+#define WM831X_DCMP3_SRC_SHIFT 13 /* DCMP3_SRC - [15:13] */
+#define WM831X_DCMP3_SRC_WIDTH 3 /* DCMP3_SRC - [15:13] */
+#define WM831X_DCMP3_GT 0x1000 /* DCMP3_GT */
+#define WM831X_DCMP3_GT_MASK 0x1000 /* DCMP3_GT */
+#define WM831X_DCMP3_GT_SHIFT 12 /* DCMP3_GT */
+#define WM831X_DCMP3_GT_WIDTH 1 /* DCMP3_GT */
+#define WM831X_DCMP3_THR_MASK 0x0FFF /* DCMP3_THR - [11:0] */
+#define WM831X_DCMP3_THR_SHIFT 0 /* DCMP3_THR - [11:0] */
+#define WM831X_DCMP3_THR_WIDTH 12 /* DCMP3_THR - [11:0] */
+
+/*
+ * R16436 (0x4034) - Comparator 4
+ */
+#define WM831X_DCMP4_SRC_MASK 0xE000 /* DCMP4_SRC - [15:13] */
+#define WM831X_DCMP4_SRC_SHIFT 13 /* DCMP4_SRC - [15:13] */
+#define WM831X_DCMP4_SRC_WIDTH 3 /* DCMP4_SRC - [15:13] */
+#define WM831X_DCMP4_GT 0x1000 /* DCMP4_GT */
+#define WM831X_DCMP4_GT_MASK 0x1000 /* DCMP4_GT */
+#define WM831X_DCMP4_GT_SHIFT 12 /* DCMP4_GT */
+#define WM831X_DCMP4_GT_WIDTH 1 /* DCMP4_GT */
+#define WM831X_DCMP4_THR_MASK 0x0FFF /* DCMP4_THR - [11:0] */
+#define WM831X_DCMP4_THR_SHIFT 0 /* DCMP4_THR - [11:0] */
+#define WM831X_DCMP4_THR_WIDTH 12 /* DCMP4_THR - [11:0] */
+
+#define WM831X_AUX_CAL_FACTOR 0xfff
+#define WM831X_AUX_CAL_NOMINAL 0x222
+
+enum wm831x_auxadc {
+ WM831X_AUX_CAL = 15,
+ WM831X_AUX_BKUP_BATT = 10,
+ WM831X_AUX_WALL = 9,
+ WM831X_AUX_BATT = 8,
+ WM831X_AUX_USB = 7,
+ WM831X_AUX_SYSVDD = 6,
+ WM831X_AUX_BATT_TEMP = 5,
+ WM831X_AUX_CHIP_TEMP = 4,
+ WM831X_AUX_AUX4 = 3,
+ WM831X_AUX_AUX3 = 2,
+ WM831X_AUX_AUX2 = 1,
+ WM831X_AUX_AUX1 = 0,
+};
+
+int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input);
+int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input);
+
+#endif
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
new file mode 100644
index 00000000000..91eb493bf14
--- /dev/null
+++ b/include/linux/mfd/wm831x/core.h
@@ -0,0 +1,289 @@
+/*
+ * include/linux/mfd/wm831x/core.h -- Core interface for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_CORE_H__
+#define __MFD_WM831X_CORE_H__
+
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+
+/*
+ * Register values.
+ */
+#define WM831X_RESET_ID 0x00
+#define WM831X_REVISION 0x01
+#define WM831X_PARENT_ID 0x4000
+#define WM831X_SYSVDD_CONTROL 0x4001
+#define WM831X_THERMAL_MONITORING 0x4002
+#define WM831X_POWER_STATE 0x4003
+#define WM831X_WATCHDOG 0x4004
+#define WM831X_ON_PIN_CONTROL 0x4005
+#define WM831X_RESET_CONTROL 0x4006
+#define WM831X_CONTROL_INTERFACE 0x4007
+#define WM831X_SECURITY_KEY 0x4008
+#define WM831X_SOFTWARE_SCRATCH 0x4009
+#define WM831X_OTP_CONTROL 0x400A
+#define WM831X_GPIO_LEVEL 0x400C
+#define WM831X_SYSTEM_STATUS 0x400D
+#define WM831X_ON_SOURCE 0x400E
+#define WM831X_OFF_SOURCE 0x400F
+#define WM831X_SYSTEM_INTERRUPTS 0x4010
+#define WM831X_INTERRUPT_STATUS_1 0x4011
+#define WM831X_INTERRUPT_STATUS_2 0x4012
+#define WM831X_INTERRUPT_STATUS_3 0x4013
+#define WM831X_INTERRUPT_STATUS_4 0x4014
+#define WM831X_INTERRUPT_STATUS_5 0x4015
+#define WM831X_IRQ_CONFIG 0x4017
+#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
+#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
+#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
+#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
+#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
+#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
+#define WM831X_RTC_WRITE_COUNTER 0x4020
+#define WM831X_RTC_TIME_1 0x4021
+#define WM831X_RTC_TIME_2 0x4022
+#define WM831X_RTC_ALARM_1 0x4023
+#define WM831X_RTC_ALARM_2 0x4024
+#define WM831X_RTC_CONTROL 0x4025
+#define WM831X_RTC_TRIM 0x4026
+#define WM831X_TOUCH_CONTROL_1 0x4028
+#define WM831X_TOUCH_CONTROL_2 0x4029
+#define WM831X_TOUCH_DATA_X 0x402A
+#define WM831X_TOUCH_DATA_Y 0x402B
+#define WM831X_TOUCH_DATA_Z 0x402C
+#define WM831X_AUXADC_DATA 0x402D
+#define WM831X_AUXADC_CONTROL 0x402E
+#define WM831X_AUXADC_SOURCE 0x402F
+#define WM831X_COMPARATOR_CONTROL 0x4030
+#define WM831X_COMPARATOR_1 0x4031
+#define WM831X_COMPARATOR_2 0x4032
+#define WM831X_COMPARATOR_3 0x4033
+#define WM831X_COMPARATOR_4 0x4034
+#define WM831X_GPIO1_CONTROL 0x4038
+#define WM831X_GPIO2_CONTROL 0x4039
+#define WM831X_GPIO3_CONTROL 0x403A
+#define WM831X_GPIO4_CONTROL 0x403B
+#define WM831X_GPIO5_CONTROL 0x403C
+#define WM831X_GPIO6_CONTROL 0x403D
+#define WM831X_GPIO7_CONTROL 0x403E
+#define WM831X_GPIO8_CONTROL 0x403F
+#define WM831X_GPIO9_CONTROL 0x4040
+#define WM831X_GPIO10_CONTROL 0x4041
+#define WM831X_GPIO11_CONTROL 0x4042
+#define WM831X_GPIO12_CONTROL 0x4043
+#define WM831X_GPIO13_CONTROL 0x4044
+#define WM831X_GPIO14_CONTROL 0x4045
+#define WM831X_GPIO15_CONTROL 0x4046
+#define WM831X_GPIO16_CONTROL 0x4047
+#define WM831X_CHARGER_CONTROL_1 0x4048
+#define WM831X_CHARGER_CONTROL_2 0x4049
+#define WM831X_CHARGER_STATUS 0x404A
+#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
+#define WM831X_STATUS_LED_1 0x404C
+#define WM831X_STATUS_LED_2 0x404D
+#define WM831X_CURRENT_SINK_1 0x404E
+#define WM831X_CURRENT_SINK_2 0x404F
+#define WM831X_DCDC_ENABLE 0x4050
+#define WM831X_LDO_ENABLE 0x4051
+#define WM831X_DCDC_STATUS 0x4052
+#define WM831X_LDO_STATUS 0x4053
+#define WM831X_DCDC_UV_STATUS 0x4054
+#define WM831X_LDO_UV_STATUS 0x4055
+#define WM831X_DC1_CONTROL_1 0x4056
+#define WM831X_DC1_CONTROL_2 0x4057
+#define WM831X_DC1_ON_CONFIG 0x4058
+#define WM831X_DC1_SLEEP_CONTROL 0x4059
+#define WM831X_DC1_DVS_CONTROL 0x405A
+#define WM831X_DC2_CONTROL_1 0x405B
+#define WM831X_DC2_CONTROL_2 0x405C
+#define WM831X_DC2_ON_CONFIG 0x405D
+#define WM831X_DC2_SLEEP_CONTROL 0x405E
+#define WM831X_DC2_DVS_CONTROL 0x405F
+#define WM831X_DC3_CONTROL_1 0x4060
+#define WM831X_DC3_CONTROL_2 0x4061
+#define WM831X_DC3_ON_CONFIG 0x4062
+#define WM831X_DC3_SLEEP_CONTROL 0x4063
+#define WM831X_DC4_CONTROL 0x4064
+#define WM831X_DC4_SLEEP_CONTROL 0x4065
+#define WM831X_EPE1_CONTROL 0x4066
+#define WM831X_EPE2_CONTROL 0x4067
+#define WM831X_LDO1_CONTROL 0x4068
+#define WM831X_LDO1_ON_CONTROL 0x4069
+#define WM831X_LDO1_SLEEP_CONTROL 0x406A
+#define WM831X_LDO2_CONTROL 0x406B
+#define WM831X_LDO2_ON_CONTROL 0x406C
+#define WM831X_LDO2_SLEEP_CONTROL 0x406D
+#define WM831X_LDO3_CONTROL 0x406E
+#define WM831X_LDO3_ON_CONTROL 0x406F
+#define WM831X_LDO3_SLEEP_CONTROL 0x4070
+#define WM831X_LDO4_CONTROL 0x4071
+#define WM831X_LDO4_ON_CONTROL 0x4072
+#define WM831X_LDO4_SLEEP_CONTROL 0x4073
+#define WM831X_LDO5_CONTROL 0x4074
+#define WM831X_LDO5_ON_CONTROL 0x4075
+#define WM831X_LDO5_SLEEP_CONTROL 0x4076
+#define WM831X_LDO6_CONTROL 0x4077
+#define WM831X_LDO6_ON_CONTROL 0x4078
+#define WM831X_LDO6_SLEEP_CONTROL 0x4079
+#define WM831X_LDO7_CONTROL 0x407A
+#define WM831X_LDO7_ON_CONTROL 0x407B
+#define WM831X_LDO7_SLEEP_CONTROL 0x407C
+#define WM831X_LDO8_CONTROL 0x407D
+#define WM831X_LDO8_ON_CONTROL 0x407E
+#define WM831X_LDO8_SLEEP_CONTROL 0x407F
+#define WM831X_LDO9_CONTROL 0x4080
+#define WM831X_LDO9_ON_CONTROL 0x4081
+#define WM831X_LDO9_SLEEP_CONTROL 0x4082
+#define WM831X_LDO10_CONTROL 0x4083
+#define WM831X_LDO10_ON_CONTROL 0x4084
+#define WM831X_LDO10_SLEEP_CONTROL 0x4085
+#define WM831X_LDO11_ON_CONTROL 0x4087
+#define WM831X_LDO11_SLEEP_CONTROL 0x4088
+#define WM831X_POWER_GOOD_SOURCE_1 0x408E
+#define WM831X_POWER_GOOD_SOURCE_2 0x408F
+#define WM831X_CLOCK_CONTROL_1 0x4090
+#define WM831X_CLOCK_CONTROL_2 0x4091
+#define WM831X_FLL_CONTROL_1 0x4092
+#define WM831X_FLL_CONTROL_2 0x4093
+#define WM831X_FLL_CONTROL_3 0x4094
+#define WM831X_FLL_CONTROL_4 0x4095
+#define WM831X_FLL_CONTROL_5 0x4096
+#define WM831X_UNIQUE_ID_1 0x7800
+#define WM831X_UNIQUE_ID_2 0x7801
+#define WM831X_UNIQUE_ID_3 0x7802
+#define WM831X_UNIQUE_ID_4 0x7803
+#define WM831X_UNIQUE_ID_5 0x7804
+#define WM831X_UNIQUE_ID_6 0x7805
+#define WM831X_UNIQUE_ID_7 0x7806
+#define WM831X_UNIQUE_ID_8 0x7807
+#define WM831X_FACTORY_OTP_ID 0x7808
+#define WM831X_FACTORY_OTP_1 0x7809
+#define WM831X_FACTORY_OTP_2 0x780A
+#define WM831X_FACTORY_OTP_3 0x780B
+#define WM831X_FACTORY_OTP_4 0x780C
+#define WM831X_FACTORY_OTP_5 0x780D
+#define WM831X_CUSTOMER_OTP_ID 0x7810
+#define WM831X_DC1_OTP_CONTROL 0x7811
+#define WM831X_DC2_OTP_CONTROL 0x7812
+#define WM831X_DC3_OTP_CONTROL 0x7813
+#define WM831X_LDO1_2_OTP_CONTROL 0x7814
+#define WM831X_LDO3_4_OTP_CONTROL 0x7815
+#define WM831X_LDO5_6_OTP_CONTROL 0x7816
+#define WM831X_LDO7_8_OTP_CONTROL 0x7817
+#define WM831X_LDO9_10_OTP_CONTROL 0x7818
+#define WM831X_LDO11_EPE_CONTROL 0x7819
+#define WM831X_GPIO1_OTP_CONTROL 0x781A
+#define WM831X_GPIO2_OTP_CONTROL 0x781B
+#define WM831X_GPIO3_OTP_CONTROL 0x781C
+#define WM831X_GPIO4_OTP_CONTROL 0x781D
+#define WM831X_GPIO5_OTP_CONTROL 0x781E
+#define WM831X_GPIO6_OTP_CONTROL 0x781F
+#define WM831X_DBE_CHECK_DATA 0x7827
+
+/*
+ * R0 (0x00) - Reset ID
+ */
+#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
+#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
+#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
+
+/*
+ * R1 (0x01) - Revision
+ */
+#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
+#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
+#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
+#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
+#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
+#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
+
+/*
+ * R16384 (0x4000) - Parent ID
+ */
+#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
+#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
+#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
+
+/*
+ * R16389 (0x4005) - ON Pin Control
+ */
+#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
+#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
+#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
+#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
+#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
+#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
+#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
+#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
+#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
+#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
+#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
+#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
+#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
+
+struct regulator_dev;
+
+struct wm831x {
+ struct mutex io_lock;
+
+ struct device *dev;
+ int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
+ int bytes, void *dest);
+ int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
+ int bytes, void *src);
+
+ void *control_data;
+
+ int irq; /* Our chip IRQ */
+ struct mutex irq_lock;
+ struct workqueue_struct *irq_wq;
+ struct work_struct irq_work;
+ unsigned int irq_base;
+ int irq_masks[5];
+
+ struct mutex auxadc_lock;
+
+ /* The WM831x has a security key blocking access to certain
+ * registers. The mutex is taken by the accessors for locking
+ * and unlocking the security key, locked is used to fail
+ * writes if the lock is held.
+ */
+ struct mutex key_lock;
+ unsigned int locked:1;
+};
+
+/* Device I/O API */
+int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
+int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
+ unsigned short val);
+void wm831x_reg_lock(struct wm831x *wm831x);
+int wm831x_reg_unlock(struct wm831x *wm831x);
+int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
+ unsigned short mask, unsigned short val);
+int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
+ int count, u16 *buf);
+
+int wm831x_irq_init(struct wm831x *wm831x, int irq);
+void wm831x_irq_exit(struct wm831x *wm831x);
+
+int __must_check wm831x_request_irq(struct wm831x *wm831x,
+ unsigned int irq, irq_handler_t handler,
+ unsigned long flags, const char *name,
+ void *dev);
+void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
+void wm831x_disable_irq(struct wm831x *wm831x, int irq);
+void wm831x_enable_irq(struct wm831x *wm831x, int irq);
+
+#endif
diff --git a/include/linux/mfd/wm831x/gpio.h b/include/linux/mfd/wm831x/gpio.h
new file mode 100644
index 00000000000..2835614af0e
--- /dev/null
+++ b/include/linux/mfd/wm831x/gpio.h
@@ -0,0 +1,55 @@
+/*
+ * include/linux/mfd/wm831x/gpio.h -- GPIO for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_GPIO_H__
+#define __MFD_WM831X_GPIO_H__
+
+/*
+ * R16440-16455 (0x4038-0x4047) - GPIOx Control
+ */
+#define WM831X_GPN_DIR 0x8000 /* GPN_DIR */
+#define WM831X_GPN_DIR_MASK 0x8000 /* GPN_DIR */
+#define WM831X_GPN_DIR_SHIFT 15 /* GPN_DIR */
+#define WM831X_GPN_DIR_WIDTH 1 /* GPN_DIR */
+#define WM831X_GPN_PULL_MASK 0x6000 /* GPN_PULL - [14:13] */
+#define WM831X_GPN_PULL_SHIFT 13 /* GPN_PULL - [14:13] */
+#define WM831X_GPN_PULL_WIDTH 2 /* GPN_PULL - [14:13] */
+#define WM831X_GPN_INT_MODE 0x1000 /* GPN_INT_MODE */
+#define WM831X_GPN_INT_MODE_MASK 0x1000 /* GPN_INT_MODE */
+#define WM831X_GPN_INT_MODE_SHIFT 12 /* GPN_INT_MODE */
+#define WM831X_GPN_INT_MODE_WIDTH 1 /* GPN_INT_MODE */
+#define WM831X_GPN_PWR_DOM 0x0800 /* GPN_PWR_DOM */
+#define WM831X_GPN_PWR_DOM_MASK 0x0800 /* GPN_PWR_DOM */
+#define WM831X_GPN_PWR_DOM_SHIFT 11 /* GPN_PWR_DOM */
+#define WM831X_GPN_PWR_DOM_WIDTH 1 /* GPN_PWR_DOM */
+#define WM831X_GPN_POL 0x0400 /* GPN_POL */
+#define WM831X_GPN_POL_MASK 0x0400 /* GPN_POL */
+#define WM831X_GPN_POL_SHIFT 10 /* GPN_POL */
+#define WM831X_GPN_POL_WIDTH 1 /* GPN_POL */
+#define WM831X_GPN_OD 0x0200 /* GPN_OD */
+#define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */
+#define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */
+#define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */
+#define WM831X_GPN_TRI 0x0080 /* GPN_TRI */
+#define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */
+#define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */
+#define WM831X_GPN_TRI_WIDTH 1 /* GPN_TRI */
+#define WM831X_GPN_FN_MASK 0x000F /* GPN_FN - [3:0] */
+#define WM831X_GPN_FN_SHIFT 0 /* GPN_FN - [3:0] */
+#define WM831X_GPN_FN_WIDTH 4 /* GPN_FN - [3:0] */
+
+#define WM831X_GPIO_PULL_NONE (0 << WM831X_GPN_PULL_SHIFT)
+#define WM831X_GPIO_PULL_DOWN (1 << WM831X_GPN_PULL_SHIFT)
+#define WM831X_GPIO_PULL_UP (2 << WM831X_GPN_PULL_SHIFT)
+#endif
diff --git a/include/linux/mfd/wm831x/irq.h b/include/linux/mfd/wm831x/irq.h
new file mode 100644
index 00000000000..3a8c97656fd
--- /dev/null
+++ b/include/linux/mfd/wm831x/irq.h
@@ -0,0 +1,764 @@
+/*
+ * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_IRQ_H__
+#define __MFD_WM831X_IRQ_H__
+
+/* Interrupt number assignments within Linux */
+#define WM831X_IRQ_TEMP_THW 0
+#define WM831X_IRQ_GPIO_1 1
+#define WM831X_IRQ_GPIO_2 2
+#define WM831X_IRQ_GPIO_3 3
+#define WM831X_IRQ_GPIO_4 4
+#define WM831X_IRQ_GPIO_5 5
+#define WM831X_IRQ_GPIO_6 6
+#define WM831X_IRQ_GPIO_7 7
+#define WM831X_IRQ_GPIO_8 8
+#define WM831X_IRQ_GPIO_9 9
+#define WM831X_IRQ_GPIO_10 10
+#define WM831X_IRQ_GPIO_11 11
+#define WM831X_IRQ_GPIO_12 12
+#define WM831X_IRQ_GPIO_13 13
+#define WM831X_IRQ_GPIO_14 14
+#define WM831X_IRQ_GPIO_15 15
+#define WM831X_IRQ_GPIO_16 16
+#define WM831X_IRQ_ON 17
+#define WM831X_IRQ_PPM_SYSLO 18
+#define WM831X_IRQ_PPM_PWR_SRC 19
+#define WM831X_IRQ_PPM_USB_CURR 20
+#define WM831X_IRQ_WDOG_TO 21
+#define WM831X_IRQ_RTC_PER 22
+#define WM831X_IRQ_RTC_ALM 23
+#define WM831X_IRQ_CHG_BATT_HOT 24
+#define WM831X_IRQ_CHG_BATT_COLD 25
+#define WM831X_IRQ_CHG_BATT_FAIL 26
+#define WM831X_IRQ_CHG_OV 27
+#define WM831X_IRQ_CHG_END 29
+#define WM831X_IRQ_CHG_TO 30
+#define WM831X_IRQ_CHG_MODE 31
+#define WM831X_IRQ_CHG_START 32
+#define WM831X_IRQ_TCHDATA 33
+#define WM831X_IRQ_TCHPD 34
+#define WM831X_IRQ_AUXADC_DATA 35
+#define WM831X_IRQ_AUXADC_DCOMP1 36
+#define WM831X_IRQ_AUXADC_DCOMP2 37
+#define WM831X_IRQ_AUXADC_DCOMP3 38
+#define WM831X_IRQ_AUXADC_DCOMP4 39
+#define WM831X_IRQ_CS1 40
+#define WM831X_IRQ_CS2 41
+#define WM831X_IRQ_HC_DC1 42
+#define WM831X_IRQ_HC_DC2 43
+#define WM831X_IRQ_UV_LDO1 44
+#define WM831X_IRQ_UV_LDO2 45
+#define WM831X_IRQ_UV_LDO3 46
+#define WM831X_IRQ_UV_LDO4 47
+#define WM831X_IRQ_UV_LDO5 48
+#define WM831X_IRQ_UV_LDO6 49
+#define WM831X_IRQ_UV_LDO7 50
+#define WM831X_IRQ_UV_LDO8 51
+#define WM831X_IRQ_UV_LDO9 52
+#define WM831X_IRQ_UV_LDO10 53
+#define WM831X_IRQ_UV_DC1 54
+#define WM831X_IRQ_UV_DC2 55
+#define WM831X_IRQ_UV_DC3 56
+#define WM831X_IRQ_UV_DC4 57
+
+#define WM831X_NUM_IRQS 58
+
+/*
+ * R16400 (0x4010) - System Interrupts
+ */
+#define WM831X_PS_INT 0x8000 /* PS_INT */
+#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
+#define WM831X_PS_INT_SHIFT 15 /* PS_INT */
+#define WM831X_PS_INT_WIDTH 1 /* PS_INT */
+#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
+#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
+#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */
+#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */
+#define WM831X_GP_INT 0x2000 /* GP_INT */
+#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
+#define WM831X_GP_INT_SHIFT 13 /* GP_INT */
+#define WM831X_GP_INT_WIDTH 1 /* GP_INT */
+#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
+#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
+#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */
+#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */
+#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
+#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
+#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */
+#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */
+#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
+#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
+#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */
+#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */
+#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
+#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
+#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */
+#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */
+#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
+#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
+#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */
+#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */
+#define WM831X_PPM_INT 0x0080 /* PPM_INT */
+#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
+#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */
+#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */
+#define WM831X_CS_INT 0x0040 /* CS_INT */
+#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
+#define WM831X_CS_INT_SHIFT 6 /* CS_INT */
+#define WM831X_CS_INT_WIDTH 1 /* CS_INT */
+#define WM831X_RTC_INT 0x0020 /* RTC_INT */
+#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
+#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */
+#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */
+#define WM831X_OTP_INT 0x0010 /* OTP_INT */
+#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
+#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */
+#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */
+#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
+#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
+#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */
+#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */
+#define WM831X_CHG_INT 0x0004 /* CHG_INT */
+#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
+#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */
+#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */
+#define WM831X_HC_INT 0x0002 /* HC_INT */
+#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
+#define WM831X_HC_INT_SHIFT 1 /* HC_INT */
+#define WM831X_HC_INT_WIDTH 1 /* HC_INT */
+#define WM831X_UV_INT 0x0001 /* UV_INT */
+#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
+#define WM831X_UV_INT_SHIFT 0 /* UV_INT */
+#define WM831X_UV_INT_WIDTH 1 /* UV_INT */
+
+/*
+ * R16401 (0x4011) - Interrupt Status 1
+ */
+#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
+#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
+#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */
+#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */
+#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
+#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
+#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */
+#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */
+#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
+#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
+#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */
+#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */
+#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
+#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
+#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */
+#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */
+#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
+#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
+#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */
+#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */
+#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
+#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
+#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */
+#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */
+#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
+#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
+#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */
+#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */
+#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
+#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
+#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */
+#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */
+#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
+#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
+#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */
+#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */
+#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
+#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
+#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */
+#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */
+#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
+#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
+#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */
+#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */
+#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
+#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
+#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */
+#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */
+#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
+#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
+#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */
+#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */
+#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
+#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
+#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */
+#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */
+#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
+#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
+#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */
+#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */
+
+/*
+ * R16402 (0x4012) - Interrupt Status 2
+ */
+#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
+#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
+#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */
+#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */
+#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
+#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
+#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */
+#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */
+#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
+#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
+#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */
+#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */
+#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
+#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
+#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */
+#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */
+#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
+#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
+#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */
+#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */
+#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
+#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
+#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */
+#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */
+#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
+#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
+#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */
+#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */
+#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
+#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
+#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */
+#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */
+#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
+#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
+#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */
+#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */
+#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
+#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
+#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */
+#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */
+#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
+#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
+#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */
+#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */
+#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
+#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
+#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */
+#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */
+#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
+#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
+#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */
+#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */
+#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
+#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
+#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */
+#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */
+#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
+#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
+#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
+#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */
+
+/*
+ * R16403 (0x4013) - Interrupt Status 3
+ */
+#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
+#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
+#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */
+#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */
+#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
+#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
+#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */
+#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */
+#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
+#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
+#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */
+#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */
+#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
+#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
+#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */
+#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */
+#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
+#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
+#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */
+#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */
+#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
+#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
+#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */
+#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */
+#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
+#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
+#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */
+#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */
+#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
+#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
+#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */
+#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */
+#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
+#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
+#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */
+#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */
+#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
+#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
+#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
+#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */
+
+/*
+ * R16404 (0x4014) - Interrupt Status 4
+ */
+#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
+#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
+#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */
+#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */
+#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
+#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
+#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */
+#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */
+#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
+#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
+#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */
+#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */
+#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
+#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
+#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */
+#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */
+#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
+#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
+#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */
+#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */
+#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
+#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
+#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
+#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */
+
+/*
+ * R16405 (0x4015) - Interrupt Status 5
+ */
+#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
+#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
+#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */
+#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */
+#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
+#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
+#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */
+#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */
+#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
+#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
+#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */
+#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */
+#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
+#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
+#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */
+#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */
+#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
+#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
+#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */
+#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */
+#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
+#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
+#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */
+#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */
+#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
+#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
+#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */
+#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */
+#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
+#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
+#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */
+#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */
+#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
+#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
+#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */
+#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */
+#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
+#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
+#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */
+#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */
+#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
+#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
+#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */
+#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */
+#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
+#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
+#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */
+#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */
+#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
+#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
+#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */
+#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */
+#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
+#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
+#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */
+#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */
+#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
+#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
+#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */
+#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */
+#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
+#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
+#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
+#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */
+
+/*
+ * R16407 (0x4017) - IRQ Config
+ */
+#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
+#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
+#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */
+#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */
+#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
+#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
+#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
+#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */
+
+/*
+ * R16408 (0x4018) - System Interrupts Mask
+ */
+#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
+#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
+#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */
+#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */
+#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
+#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
+#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */
+#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */
+#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
+#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
+#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */
+#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */
+#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
+#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
+#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */
+#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */
+#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
+#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
+#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */
+#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */
+#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
+#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
+#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */
+#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */
+#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
+#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
+#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */
+#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */
+#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
+#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
+#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */
+#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */
+#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
+#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
+#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */
+#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */
+#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
+#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
+#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */
+#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */
+#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
+#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
+#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */
+#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */
+#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
+#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
+#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */
+#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */
+#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
+#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
+#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */
+#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */
+#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
+#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
+#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */
+#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */
+#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
+#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
+#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */
+#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */
+#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
+#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
+#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
+#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */
+
+/*
+ * R16409 (0x4019) - Interrupt Status 1 Mask
+ */
+#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
+#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
+#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */
+#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */
+#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
+#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
+#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */
+#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */
+#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
+#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
+#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */
+#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */
+#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
+#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
+#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */
+#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */
+#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
+#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
+#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */
+#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */
+#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
+#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
+#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */
+#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */
+#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
+#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
+#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */
+#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */
+#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
+#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
+#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */
+#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */
+#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
+#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
+#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */
+#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */
+#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
+#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
+#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */
+#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */
+#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
+#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
+#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */
+#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */
+#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
+#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
+#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */
+#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */
+#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
+#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
+#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */
+#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */
+#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
+#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
+#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */
+#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */
+#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
+#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
+#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */
+#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */
+
+/*
+ * R16410 (0x401A) - Interrupt Status 2 Mask
+ */
+#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
+#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
+#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */
+#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */
+#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
+#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
+#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */
+#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */
+#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
+#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
+#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */
+#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */
+#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
+#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
+#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */
+#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */
+#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
+#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
+#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */
+#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */
+#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
+#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
+#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */
+#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */
+#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
+#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
+#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */
+#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */
+#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
+#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
+#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */
+#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */
+#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
+#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
+#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */
+#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */
+#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
+#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
+#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */
+#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */
+#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
+#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
+#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */
+#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */
+#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
+#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
+#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */
+#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */
+#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
+#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
+#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */
+#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */
+#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
+#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
+#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */
+#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */
+#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
+#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
+#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
+#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */
+
+/*
+ * R16411 (0x401B) - Interrupt Status 3 Mask
+ */
+#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
+#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
+#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */
+#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */
+#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
+#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
+#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */
+#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */
+#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
+#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
+#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */
+#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */
+#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
+#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
+#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */
+#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */
+#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
+#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
+#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */
+#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */
+#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
+#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
+#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */
+#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */
+#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
+#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
+#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */
+#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */
+#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
+#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
+#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */
+#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */
+#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
+#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
+#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */
+#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */
+#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
+#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
+#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
+#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */
+
+/*
+ * R16412 (0x401C) - Interrupt Status 4 Mask
+ */
+#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
+#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
+#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */
+#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */
+#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
+#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
+#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */
+#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */
+#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
+#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
+#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */
+#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */
+#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
+#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
+#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */
+#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */
+#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
+#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
+#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */
+#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */
+#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
+#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
+#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
+#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */
+
+/*
+ * R16413 (0x401D) - Interrupt Status 5 Mask
+ */
+#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
+#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
+#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */
+#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */
+#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
+#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
+#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */
+#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */
+#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
+#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
+#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
+#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
+#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
+#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
+#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
+#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
+#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
+#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
+#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
+#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
+#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
+#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
+#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
+#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
+#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
+#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
+#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
+#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
+#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
+#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
+#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
+#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
+#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
+#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
+#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
+#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
+#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
+#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
+#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
+#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
+#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
+#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
+#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
+#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
+#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
+#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
+#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
+#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
+#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
+#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
+#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
+#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
+#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
+#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
+#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
+#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
+#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
+#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
+#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
+#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
+#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
+#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
+#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
+#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
+
+
+#endif
diff --git a/include/linux/mfd/wm831x/otp.h b/include/linux/mfd/wm831x/otp.h
new file mode 100644
index 00000000000..ce1f81a39bf
--- /dev/null
+++ b/include/linux/mfd/wm831x/otp.h
@@ -0,0 +1,162 @@
+/*
+ * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_OTP_H__
+#define __MFD_WM831X_OTP_H__
+
+int wm831x_otp_init(struct wm831x *wm831x);
+void wm831x_otp_exit(struct wm831x *wm831x);
+
+/*
+ * R30720 (0x7800) - Unique ID 1
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30721 (0x7801) - Unique ID 2
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30722 (0x7802) - Unique ID 3
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30723 (0x7803) - Unique ID 4
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30724 (0x7804) - Unique ID 5
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30725 (0x7805) - Unique ID 6
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30726 (0x7806) - Unique ID 7
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30727 (0x7807) - Unique ID 8
+ */
+#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
+#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
+
+/*
+ * R30728 (0x7808) - Factory OTP ID
+ */
+#define WM831X_OTP_FACT_ID_MASK 0xFFFE /* OTP_FACT_ID - [15:1] */
+#define WM831X_OTP_FACT_ID_SHIFT 1 /* OTP_FACT_ID - [15:1] */
+#define WM831X_OTP_FACT_ID_WIDTH 15 /* OTP_FACT_ID - [15:1] */
+#define WM831X_OTP_FACT_FINAL 0x0001 /* OTP_FACT_FINAL */
+#define WM831X_OTP_FACT_FINAL_MASK 0x0001 /* OTP_FACT_FINAL */
+#define WM831X_OTP_FACT_FINAL_SHIFT 0 /* OTP_FACT_FINAL */
+#define WM831X_OTP_FACT_FINAL_WIDTH 1 /* OTP_FACT_FINAL */
+
+/*
+ * R30729 (0x7809) - Factory OTP 1
+ */
+#define WM831X_DC3_TRIM_MASK 0xF000 /* DC3_TRIM - [15:12] */
+#define WM831X_DC3_TRIM_SHIFT 12 /* DC3_TRIM - [15:12] */
+#define WM831X_DC3_TRIM_WIDTH 4 /* DC3_TRIM - [15:12] */
+#define WM831X_DC2_TRIM_MASK 0x0FC0 /* DC2_TRIM - [11:6] */
+#define WM831X_DC2_TRIM_SHIFT 6 /* DC2_TRIM - [11:6] */
+#define WM831X_DC2_TRIM_WIDTH 6 /* DC2_TRIM - [11:6] */
+#define WM831X_DC1_TRIM_MASK 0x003F /* DC1_TRIM - [5:0] */
+#define WM831X_DC1_TRIM_SHIFT 0 /* DC1_TRIM - [5:0] */
+#define WM831X_DC1_TRIM_WIDTH 6 /* DC1_TRIM - [5:0] */
+
+/*
+ * R30730 (0x780A) - Factory OTP 2
+ */
+#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
+#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
+#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
+
+/*
+ * R30731 (0x780B) - Factory OTP 3
+ */
+#define WM831X_OSC_TRIM_MASK 0x0780 /* OSC_TRIM - [10:7] */
+#define WM831X_OSC_TRIM_SHIFT 7 /* OSC_TRIM - [10:7] */
+#define WM831X_OSC_TRIM_WIDTH 4 /* OSC_TRIM - [10:7] */
+#define WM831X_BG_TRIM_MASK 0x0078 /* BG_TRIM - [6:3] */
+#define WM831X_BG_TRIM_SHIFT 3 /* BG_TRIM - [6:3] */
+#define WM831X_BG_TRIM_WIDTH 4 /* BG_TRIM - [6:3] */
+#define WM831X_LPBG_TRIM_MASK 0x0007 /* LPBG_TRIM - [2:0] */
+#define WM831X_LPBG_TRIM_SHIFT 0 /* LPBG_TRIM - [2:0] */
+#define WM831X_LPBG_TRIM_WIDTH 3 /* LPBG_TRIM - [2:0] */
+
+/*
+ * R30732 (0x780C) - Factory OTP 4
+ */
+#define WM831X_CHILD_I2C_ADDR_MASK 0x00FE /* CHILD_I2C_ADDR - [7:1] */
+#define WM831X_CHILD_I2C_ADDR_SHIFT 1 /* CHILD_I2C_ADDR - [7:1] */
+#define WM831X_CHILD_I2C_ADDR_WIDTH 7 /* CHILD_I2C_ADDR - [7:1] */
+#define WM831X_CH_AW 0x0001 /* CH_AW */
+#define WM831X_CH_AW_MASK 0x0001 /* CH_AW */
+#define WM831X_CH_AW_SHIFT 0 /* CH_AW */
+#define WM831X_CH_AW_WIDTH 1 /* CH_AW */
+
+/*
+ * R30733 (0x780D) - Factory OTP 5
+ */
+#define WM831X_CHARGE_TRIM_MASK 0x003F /* CHARGE_TRIM - [5:0] */
+#define WM831X_CHARGE_TRIM_SHIFT 0 /* CHARGE_TRIM - [5:0] */
+#define WM831X_CHARGE_TRIM_WIDTH 6 /* CHARGE_TRIM - [5:0] */
+
+/*
+ * R30736 (0x7810) - Customer OTP ID
+ */
+#define WM831X_OTP_AUTO_PROG 0x8000 /* OTP_AUTO_PROG */
+#define WM831X_OTP_AUTO_PROG_MASK 0x8000 /* OTP_AUTO_PROG */
+#define WM831X_OTP_AUTO_PROG_SHIFT 15 /* OTP_AUTO_PROG */
+#define WM831X_OTP_AUTO_PROG_WIDTH 1 /* OTP_AUTO_PROG */
+#define WM831X_OTP_CUST_ID_MASK 0x7FFE /* OTP_CUST_ID - [14:1] */
+#define WM831X_OTP_CUST_ID_SHIFT 1 /* OTP_CUST_ID - [14:1] */
+#define WM831X_OTP_CUST_ID_WIDTH 14 /* OTP_CUST_ID - [14:1] */
+#define WM831X_OTP_CUST_FINAL 0x0001 /* OTP_CUST_FINAL */
+#define WM831X_OTP_CUST_FINAL_MASK 0x0001 /* OTP_CUST_FINAL */
+#define WM831X_OTP_CUST_FINAL_SHIFT 0 /* OTP_CUST_FINAL */
+#define WM831X_OTP_CUST_FINAL_WIDTH 1 /* OTP_CUST_FINAL */
+
+/*
+ * R30759 (0x7827) - DBE CHECK DATA
+ */
+#define WM831X_DBE_VALID_DATA_MASK 0xFFFF /* DBE_VALID_DATA - [15:0] */
+#define WM831X_DBE_VALID_DATA_SHIFT 0 /* DBE_VALID_DATA - [15:0] */
+#define WM831X_DBE_VALID_DATA_WIDTH 16 /* DBE_VALID_DATA - [15:0] */
+
+
+#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
new file mode 100644
index 00000000000..90d820260aa
--- /dev/null
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -0,0 +1,113 @@
+/*
+ * include/linux/mfd/wm831x/pdata.h -- Platform data for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_PDATA_H__
+#define __MFD_WM831X_PDATA_H__
+
+struct wm831x;
+struct regulator_init_data;
+
+struct wm831x_backlight_pdata {
+ int isink; /** ISINK to use, 1 or 2 */
+ int max_uA; /** Maximum current to allow */
+};
+
+struct wm831x_backup_pdata {
+ int charger_enable;
+ int no_constant_voltage; /** Disable constant voltage charging */
+ int vlim; /** Voltage limit in milivolts */
+ int ilim; /** Current limit in microamps */
+};
+
+struct wm831x_battery_pdata {
+ int enable; /** Enable charging */
+ int fast_enable; /** Enable fast charging */
+ int off_mask; /** Mask OFF while charging */
+ int trickle_ilim; /** Trickle charge current limit, in mA */
+ int vsel; /** Target voltage, in mV */
+ int eoc_iterm; /** End of trickle charge current, in mA */
+ int fast_ilim; /** Fast charge current limit, in mA */
+ int timeout; /** Charge cycle timeout, in minutes */
+};
+
+/* Sources for status LED configuration. Values are register values
+ * plus 1 to allow for a zero default for preserve.
+ */
+enum wm831x_status_src {
+ WM831X_STATUS_PRESERVE = 0, /* Keep the current hardware setting */
+ WM831X_STATUS_OTP = 1,
+ WM831X_STATUS_POWER = 2,
+ WM831X_STATUS_CHARGER = 3,
+ WM831X_STATUS_MANUAL = 4,
+};
+
+struct wm831x_status_pdata {
+ enum wm831x_status_src default_src;
+ const char *name;
+ const char *default_trigger;
+};
+
+struct wm831x_touch_pdata {
+ int fivewire; /** 1 for five wire mode, 0 for 4 wire */
+ int isel; /** Current for pen down (uA) */
+ int rpu; /** Pen down sensitivity resistor divider */
+ int pressure; /** Report pressure (boolean) */
+ int data_irq; /** Touch data ready IRQ */
+};
+
+enum wm831x_watchdog_action {
+ WM831X_WDOG_NONE = 0,
+ WM831X_WDOG_INTERRUPT = 1,
+ WM831X_WDOG_RESET = 2,
+ WM831X_WDOG_WAKE = 3,
+};
+
+struct wm831x_watchdog_pdata {
+ enum wm831x_watchdog_action primary, secondary;
+ int update_gpio;
+ unsigned int software:1;
+};
+
+#define WM831X_MAX_STATUS 2
+#define WM831X_MAX_DCDC 4
+#define WM831X_MAX_EPE 2
+#define WM831X_MAX_LDO 11
+#define WM831X_MAX_ISINK 2
+
+struct wm831x_pdata {
+ /** Called before subdevices are set up */
+ int (*pre_init)(struct wm831x *wm831x);
+ /** Called after subdevices are set up */
+ int (*post_init)(struct wm831x *wm831x);
+
+ int gpio_base;
+ struct wm831x_backlight_pdata *backlight;
+ struct wm831x_backup_pdata *backup;
+ struct wm831x_battery_pdata *battery;
+ struct wm831x_touch_pdata *touch;
+ struct wm831x_watchdog_pdata *watchdog;
+
+ /** LED1 = 0 and so on */
+ struct wm831x_status_pdata *status[WM831X_MAX_STATUS];
+ /** DCDC1 = 0 and so on */
+ struct regulator_init_data *dcdc[WM831X_MAX_DCDC];
+ /** EPE1 = 0 and so on */
+ struct regulator_init_data *epe[WM831X_MAX_EPE];
+ /** LDO1 = 0 and so on */
+ struct regulator_init_data *ldo[WM831X_MAX_LDO];
+ /** ISINK1 = 0 and so on*/
+ struct regulator_init_data *isink[WM831X_MAX_ISINK];
+};
+
+#endif
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
new file mode 100644
index 00000000000..f95466343fb
--- /dev/null
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -0,0 +1,1218 @@
+/*
+ * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_REGULATOR_H__
+#define __MFD_WM831X_REGULATOR_H__
+
+/*
+ * R16462 (0x404E) - Current Sink 1
+ */
+#define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
+#define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
+#define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
+#define WM831X_CS1_ENA_WIDTH 1 /* CS1_ENA */
+#define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
+#define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
+#define WM831X_CS1_DRIVE_SHIFT 14 /* CS1_DRIVE */
+#define WM831X_CS1_DRIVE_WIDTH 1 /* CS1_DRIVE */
+#define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
+#define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
+#define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */
+#define WM831X_CS1_SLPENA_WIDTH 1 /* CS1_SLPENA */
+#define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
+#define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */
+#define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */
+#define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
+#define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */
+#define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */
+#define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
+#define WM831X_CS1_ISEL_SHIFT 0 /* CS1_ISEL - [5:0] */
+#define WM831X_CS1_ISEL_WIDTH 6 /* CS1_ISEL - [5:0] */
+
+/*
+ * R16463 (0x404F) - Current Sink 2
+ */
+#define WM831X_CS2_ENA 0x8000 /* CS2_ENA */
+#define WM831X_CS2_ENA_MASK 0x8000 /* CS2_ENA */
+#define WM831X_CS2_ENA_SHIFT 15 /* CS2_ENA */
+#define WM831X_CS2_ENA_WIDTH 1 /* CS2_ENA */
+#define WM831X_CS2_DRIVE 0x4000 /* CS2_DRIVE */
+#define WM831X_CS2_DRIVE_MASK 0x4000 /* CS2_DRIVE */
+#define WM831X_CS2_DRIVE_SHIFT 14 /* CS2_DRIVE */
+#define WM831X_CS2_DRIVE_WIDTH 1 /* CS2_DRIVE */
+#define WM831X_CS2_SLPENA 0x1000 /* CS2_SLPENA */
+#define WM831X_CS2_SLPENA_MASK 0x1000 /* CS2_SLPENA */
+#define WM831X_CS2_SLPENA_SHIFT 12 /* CS2_SLPENA */
+#define WM831X_CS2_SLPENA_WIDTH 1 /* CS2_SLPENA */
+#define WM831X_CS2_OFF_RAMP_MASK 0x0C00 /* CS2_OFF_RAMP - [11:10] */
+#define WM831X_CS2_OFF_RAMP_SHIFT 10 /* CS2_OFF_RAMP - [11:10] */
+#define WM831X_CS2_OFF_RAMP_WIDTH 2 /* CS2_OFF_RAMP - [11:10] */
+#define WM831X_CS2_ON_RAMP_MASK 0x0300 /* CS2_ON_RAMP - [9:8] */
+#define WM831X_CS2_ON_RAMP_SHIFT 8 /* CS2_ON_RAMP - [9:8] */
+#define WM831X_CS2_ON_RAMP_WIDTH 2 /* CS2_ON_RAMP - [9:8] */
+#define WM831X_CS2_ISEL_MASK 0x003F /* CS2_ISEL - [5:0] */
+#define WM831X_CS2_ISEL_SHIFT 0 /* CS2_ISEL - [5:0] */
+#define WM831X_CS2_ISEL_WIDTH 6 /* CS2_ISEL - [5:0] */
+
+/*
+ * R16464 (0x4050) - DCDC Enable
+ */
+#define WM831X_EPE2_ENA 0x0080 /* EPE2_ENA */
+#define WM831X_EPE2_ENA_MASK 0x0080 /* EPE2_ENA */
+#define WM831X_EPE2_ENA_SHIFT 7 /* EPE2_ENA */
+#define WM831X_EPE2_ENA_WIDTH 1 /* EPE2_ENA */
+#define WM831X_EPE1_ENA 0x0040 /* EPE1_ENA */
+#define WM831X_EPE1_ENA_MASK 0x0040 /* EPE1_ENA */
+#define WM831X_EPE1_ENA_SHIFT 6 /* EPE1_ENA */
+#define WM831X_EPE1_ENA_WIDTH 1 /* EPE1_ENA */
+#define WM831X_DC4_ENA 0x0008 /* DC4_ENA */
+#define WM831X_DC4_ENA_MASK 0x0008 /* DC4_ENA */
+#define WM831X_DC4_ENA_SHIFT 3 /* DC4_ENA */
+#define WM831X_DC4_ENA_WIDTH 1 /* DC4_ENA */
+#define WM831X_DC3_ENA 0x0004 /* DC3_ENA */
+#define WM831X_DC3_ENA_MASK 0x0004 /* DC3_ENA */
+#define WM831X_DC3_ENA_SHIFT 2 /* DC3_ENA */
+#define WM831X_DC3_ENA_WIDTH 1 /* DC3_ENA */
+#define WM831X_DC2_ENA 0x0002 /* DC2_ENA */
+#define WM831X_DC2_ENA_MASK 0x0002 /* DC2_ENA */
+#define WM831X_DC2_ENA_SHIFT 1 /* DC2_ENA */
+#define WM831X_DC2_ENA_WIDTH 1 /* DC2_ENA */
+#define WM831X_DC1_ENA 0x0001 /* DC1_ENA */
+#define WM831X_DC1_ENA_MASK 0x0001 /* DC1_ENA */
+#define WM831X_DC1_ENA_SHIFT 0 /* DC1_ENA */
+#define WM831X_DC1_ENA_WIDTH 1 /* DC1_ENA */
+
+/*
+ * R16465 (0x4051) - LDO Enable
+ */
+#define WM831X_LDO11_ENA 0x0400 /* LDO11_ENA */
+#define WM831X_LDO11_ENA_MASK 0x0400 /* LDO11_ENA */
+#define WM831X_LDO11_ENA_SHIFT 10 /* LDO11_ENA */
+#define WM831X_LDO11_ENA_WIDTH 1 /* LDO11_ENA */
+#define WM831X_LDO10_ENA 0x0200 /* LDO10_ENA */
+#define WM831X_LDO10_ENA_MASK 0x0200 /* LDO10_ENA */
+#define WM831X_LDO10_ENA_SHIFT 9 /* LDO10_ENA */
+#define WM831X_LDO10_ENA_WIDTH 1 /* LDO10_ENA */
+#define WM831X_LDO9_ENA 0x0100 /* LDO9_ENA */
+#define WM831X_LDO9_ENA_MASK 0x0100 /* LDO9_ENA */
+#define WM831X_LDO9_ENA_SHIFT 8 /* LDO9_ENA */
+#define WM831X_LDO9_ENA_WIDTH 1 /* LDO9_ENA */
+#define WM831X_LDO8_ENA 0x0080 /* LDO8_ENA */
+#define WM831X_LDO8_ENA_MASK 0x0080 /* LDO8_ENA */
+#define WM831X_LDO8_ENA_SHIFT 7 /* LDO8_ENA */
+#define WM831X_LDO8_ENA_WIDTH 1 /* LDO8_ENA */
+#define WM831X_LDO7_ENA 0x0040 /* LDO7_ENA */
+#define WM831X_LDO7_ENA_MASK 0x0040 /* LDO7_ENA */
+#define WM831X_LDO7_ENA_SHIFT 6 /* LDO7_ENA */
+#define WM831X_LDO7_ENA_WIDTH 1 /* LDO7_ENA */
+#define WM831X_LDO6_ENA 0x0020 /* LDO6_ENA */
+#define WM831X_LDO6_ENA_MASK 0x0020 /* LDO6_ENA */
+#define WM831X_LDO6_ENA_SHIFT 5 /* LDO6_ENA */
+#define WM831X_LDO6_ENA_WIDTH 1 /* LDO6_ENA */
+#define WM831X_LDO5_ENA 0x0010 /* LDO5_ENA */
+#define WM831X_LDO5_ENA_MASK 0x0010 /* LDO5_ENA */
+#define WM831X_LDO5_ENA_SHIFT 4 /* LDO5_ENA */
+#define WM831X_LDO5_ENA_WIDTH 1 /* LDO5_ENA */
+#define WM831X_LDO4_ENA 0x0008 /* LDO4_ENA */
+#define WM831X_LDO4_ENA_MASK 0x0008 /* LDO4_ENA */
+#define WM831X_LDO4_ENA_SHIFT 3 /* LDO4_ENA */
+#define WM831X_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
+#define WM831X_LDO3_ENA 0x0004 /* LDO3_ENA */
+#define WM831X_LDO3_ENA_MASK 0x0004 /* LDO3_ENA */
+#define WM831X_LDO3_ENA_SHIFT 2 /* LDO3_ENA */
+#define WM831X_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
+#define WM831X_LDO2_ENA 0x0002 /* LDO2_ENA */
+#define WM831X_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
+#define WM831X_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
+#define WM831X_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
+#define WM831X_LDO1_ENA 0x0001 /* LDO1_ENA */
+#define WM831X_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
+#define WM831X_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
+#define WM831X_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
+
+/*
+ * R16466 (0x4052) - DCDC Status
+ */
+#define WM831X_EPE2_STS 0x0080 /* EPE2_STS */
+#define WM831X_EPE2_STS_MASK 0x0080 /* EPE2_STS */
+#define WM831X_EPE2_STS_SHIFT 7 /* EPE2_STS */
+#define WM831X_EPE2_STS_WIDTH 1 /* EPE2_STS */
+#define WM831X_EPE1_STS 0x0040 /* EPE1_STS */
+#define WM831X_EPE1_STS_MASK 0x0040 /* EPE1_STS */
+#define WM831X_EPE1_STS_SHIFT 6 /* EPE1_STS */
+#define WM831X_EPE1_STS_WIDTH 1 /* EPE1_STS */
+#define WM831X_DC4_STS 0x0008 /* DC4_STS */
+#define WM831X_DC4_STS_MASK 0x0008 /* DC4_STS */
+#define WM831X_DC4_STS_SHIFT 3 /* DC4_STS */
+#define WM831X_DC4_STS_WIDTH 1 /* DC4_STS */
+#define WM831X_DC3_STS 0x0004 /* DC3_STS */
+#define WM831X_DC3_STS_MASK 0x0004 /* DC3_STS */
+#define WM831X_DC3_STS_SHIFT 2 /* DC3_STS */
+#define WM831X_DC3_STS_WIDTH 1 /* DC3_STS */
+#define WM831X_DC2_STS 0x0002 /* DC2_STS */
+#define WM831X_DC2_STS_MASK 0x0002 /* DC2_STS */
+#define WM831X_DC2_STS_SHIFT 1 /* DC2_STS */
+#define WM831X_DC2_STS_WIDTH 1 /* DC2_STS */
+#define WM831X_DC1_STS 0x0001 /* DC1_STS */
+#define WM831X_DC1_STS_MASK 0x0001 /* DC1_STS */
+#define WM831X_DC1_STS_SHIFT 0 /* DC1_STS */
+#define WM831X_DC1_STS_WIDTH 1 /* DC1_STS */
+
+/*
+ * R16467 (0x4053) - LDO Status
+ */
+#define WM831X_LDO11_STS 0x0400 /* LDO11_STS */
+#define WM831X_LDO11_STS_MASK 0x0400 /* LDO11_STS */
+#define WM831X_LDO11_STS_SHIFT 10 /* LDO11_STS */
+#define WM831X_LDO11_STS_WIDTH 1 /* LDO11_STS */
+#define WM831X_LDO10_STS 0x0200 /* LDO10_STS */
+#define WM831X_LDO10_STS_MASK 0x0200 /* LDO10_STS */
+#define WM831X_LDO10_STS_SHIFT 9 /* LDO10_STS */
+#define WM831X_LDO10_STS_WIDTH 1 /* LDO10_STS */
+#define WM831X_LDO9_STS 0x0100 /* LDO9_STS */
+#define WM831X_LDO9_STS_MASK 0x0100 /* LDO9_STS */
+#define WM831X_LDO9_STS_SHIFT 8 /* LDO9_STS */
+#define WM831X_LDO9_STS_WIDTH 1 /* LDO9_STS */
+#define WM831X_LDO8_STS 0x0080 /* LDO8_STS */
+#define WM831X_LDO8_STS_MASK 0x0080 /* LDO8_STS */
+#define WM831X_LDO8_STS_SHIFT 7 /* LDO8_STS */
+#define WM831X_LDO8_STS_WIDTH 1 /* LDO8_STS */
+#define WM831X_LDO7_STS 0x0040 /* LDO7_STS */
+#define WM831X_LDO7_STS_MASK 0x0040 /* LDO7_STS */
+#define WM831X_LDO7_STS_SHIFT 6 /* LDO7_STS */
+#define WM831X_LDO7_STS_WIDTH 1 /* LDO7_STS */
+#define WM831X_LDO6_STS 0x0020 /* LDO6_STS */
+#define WM831X_LDO6_STS_MASK 0x0020 /* LDO6_STS */
+#define WM831X_LDO6_STS_SHIFT 5 /* LDO6_STS */
+#define WM831X_LDO6_STS_WIDTH 1 /* LDO6_STS */
+#define WM831X_LDO5_STS 0x0010 /* LDO5_STS */
+#define WM831X_LDO5_STS_MASK 0x0010 /* LDO5_STS */
+#define WM831X_LDO5_STS_SHIFT 4 /* LDO5_STS */
+#define WM831X_LDO5_STS_WIDTH 1 /* LDO5_STS */
+#define WM831X_LDO4_STS 0x0008 /* LDO4_STS */
+#define WM831X_LDO4_STS_MASK 0x0008 /* LDO4_STS */
+#define WM831X_LDO4_STS_SHIFT 3 /* LDO4_STS */
+#define WM831X_LDO4_STS_WIDTH 1 /* LDO4_STS */
+#define WM831X_LDO3_STS 0x0004 /* LDO3_STS */
+#define WM831X_LDO3_STS_MASK 0x0004 /* LDO3_STS */
+#define WM831X_LDO3_STS_SHIFT 2 /* LDO3_STS */
+#define WM831X_LDO3_STS_WIDTH 1 /* LDO3_STS */
+#define WM831X_LDO2_STS 0x0002 /* LDO2_STS */
+#define WM831X_LDO2_STS_MASK 0x0002 /* LDO2_STS */
+#define WM831X_LDO2_STS_SHIFT 1 /* LDO2_STS */
+#define WM831X_LDO2_STS_WIDTH 1 /* LDO2_STS */
+#define WM831X_LDO1_STS 0x0001 /* LDO1_STS */
+#define WM831X_LDO1_STS_MASK 0x0001 /* LDO1_STS */
+#define WM831X_LDO1_STS_SHIFT 0 /* LDO1_STS */
+#define WM831X_LDO1_STS_WIDTH 1 /* LDO1_STS */
+
+/*
+ * R16468 (0x4054) - DCDC UV Status
+ */
+#define WM831X_DC2_OV_STS 0x2000 /* DC2_OV_STS */
+#define WM831X_DC2_OV_STS_MASK 0x2000 /* DC2_OV_STS */
+#define WM831X_DC2_OV_STS_SHIFT 13 /* DC2_OV_STS */
+#define WM831X_DC2_OV_STS_WIDTH 1 /* DC2_OV_STS */
+#define WM831X_DC1_OV_STS 0x1000 /* DC1_OV_STS */
+#define WM831X_DC1_OV_STS_MASK 0x1000 /* DC1_OV_STS */
+#define WM831X_DC1_OV_STS_SHIFT 12 /* DC1_OV_STS */
+#define WM831X_DC1_OV_STS_WIDTH 1 /* DC1_OV_STS */
+#define WM831X_DC2_HC_STS 0x0200 /* DC2_HC_STS */
+#define WM831X_DC2_HC_STS_MASK 0x0200 /* DC2_HC_STS */
+#define WM831X_DC2_HC_STS_SHIFT 9 /* DC2_HC_STS */
+#define WM831X_DC2_HC_STS_WIDTH 1 /* DC2_HC_STS */
+#define WM831X_DC1_HC_STS 0x0100 /* DC1_HC_STS */
+#define WM831X_DC1_HC_STS_MASK 0x0100 /* DC1_HC_STS */
+#define WM831X_DC1_HC_STS_SHIFT 8 /* DC1_HC_STS */
+#define WM831X_DC1_HC_STS_WIDTH 1 /* DC1_HC_STS */
+#define WM831X_DC4_UV_STS 0x0008 /* DC4_UV_STS */
+#define WM831X_DC4_UV_STS_MASK 0x0008 /* DC4_UV_STS */
+#define WM831X_DC4_UV_STS_SHIFT 3 /* DC4_UV_STS */
+#define WM831X_DC4_UV_STS_WIDTH 1 /* DC4_UV_STS */
+#define WM831X_DC3_UV_STS 0x0004 /* DC3_UV_STS */
+#define WM831X_DC3_UV_STS_MASK 0x0004 /* DC3_UV_STS */
+#define WM831X_DC3_UV_STS_SHIFT 2 /* DC3_UV_STS */
+#define WM831X_DC3_UV_STS_WIDTH 1 /* DC3_UV_STS */
+#define WM831X_DC2_UV_STS 0x0002 /* DC2_UV_STS */
+#define WM831X_DC2_UV_STS_MASK 0x0002 /* DC2_UV_STS */
+#define WM831X_DC2_UV_STS_SHIFT 1 /* DC2_UV_STS */
+#define WM831X_DC2_UV_STS_WIDTH 1 /* DC2_UV_STS */
+#define WM831X_DC1_UV_STS 0x0001 /* DC1_UV_STS */
+#define WM831X_DC1_UV_STS_MASK 0x0001 /* DC1_UV_STS */
+#define WM831X_DC1_UV_STS_SHIFT 0 /* DC1_UV_STS */
+#define WM831X_DC1_UV_STS_WIDTH 1 /* DC1_UV_STS */
+
+/*
+ * R16469 (0x4055) - LDO UV Status
+ */
+#define WM831X_INTLDO_UV_STS 0x8000 /* INTLDO_UV_STS */
+#define WM831X_INTLDO_UV_STS_MASK 0x8000 /* INTLDO_UV_STS */
+#define WM831X_INTLDO_UV_STS_SHIFT 15 /* INTLDO_UV_STS */
+#define WM831X_INTLDO_UV_STS_WIDTH 1 /* INTLDO_UV_STS */
+#define WM831X_LDO10_UV_STS 0x0200 /* LDO10_UV_STS */
+#define WM831X_LDO10_UV_STS_MASK 0x0200 /* LDO10_UV_STS */
+#define WM831X_LDO10_UV_STS_SHIFT 9 /* LDO10_UV_STS */
+#define WM831X_LDO10_UV_STS_WIDTH 1 /* LDO10_UV_STS */
+#define WM831X_LDO9_UV_STS 0x0100 /* LDO9_UV_STS */
+#define WM831X_LDO9_UV_STS_MASK 0x0100 /* LDO9_UV_STS */
+#define WM831X_LDO9_UV_STS_SHIFT 8 /* LDO9_UV_STS */
+#define WM831X_LDO9_UV_STS_WIDTH 1 /* LDO9_UV_STS */
+#define WM831X_LDO8_UV_STS 0x0080 /* LDO8_UV_STS */
+#define WM831X_LDO8_UV_STS_MASK 0x0080 /* LDO8_UV_STS */
+#define WM831X_LDO8_UV_STS_SHIFT 7 /* LDO8_UV_STS */
+#define WM831X_LDO8_UV_STS_WIDTH 1 /* LDO8_UV_STS */
+#define WM831X_LDO7_UV_STS 0x0040 /* LDO7_UV_STS */
+#define WM831X_LDO7_UV_STS_MASK 0x0040 /* LDO7_UV_STS */
+#define WM831X_LDO7_UV_STS_SHIFT 6 /* LDO7_UV_STS */
+#define WM831X_LDO7_UV_STS_WIDTH 1 /* LDO7_UV_STS */
+#define WM831X_LDO6_UV_STS 0x0020 /* LDO6_UV_STS */
+#define WM831X_LDO6_UV_STS_MASK 0x0020 /* LDO6_UV_STS */
+#define WM831X_LDO6_UV_STS_SHIFT 5 /* LDO6_UV_STS */
+#define WM831X_LDO6_UV_STS_WIDTH 1 /* LDO6_UV_STS */
+#define WM831X_LDO5_UV_STS 0x0010 /* LDO5_UV_STS */
+#define WM831X_LDO5_UV_STS_MASK 0x0010 /* LDO5_UV_STS */
+#define WM831X_LDO5_UV_STS_SHIFT 4 /* LDO5_UV_STS */
+#define WM831X_LDO5_UV_STS_WIDTH 1 /* LDO5_UV_STS */
+#define WM831X_LDO4_UV_STS 0x0008 /* LDO4_UV_STS */
+#define WM831X_LDO4_UV_STS_MASK 0x0008 /* LDO4_UV_STS */
+#define WM831X_LDO4_UV_STS_SHIFT 3 /* LDO4_UV_STS */
+#define WM831X_LDO4_UV_STS_WIDTH 1 /* LDO4_UV_STS */
+#define WM831X_LDO3_UV_STS 0x0004 /* LDO3_UV_STS */
+#define WM831X_LDO3_UV_STS_MASK 0x0004 /* LDO3_UV_STS */
+#define WM831X_LDO3_UV_STS_SHIFT 2 /* LDO3_UV_STS */
+#define WM831X_LDO3_UV_STS_WIDTH 1 /* LDO3_UV_STS */
+#define WM831X_LDO2_UV_STS 0x0002 /* LDO2_UV_STS */
+#define WM831X_LDO2_UV_STS_MASK 0x0002 /* LDO2_UV_STS */
+#define WM831X_LDO2_UV_STS_SHIFT 1 /* LDO2_UV_STS */
+#define WM831X_LDO2_UV_STS_WIDTH 1 /* LDO2_UV_STS */
+#define WM831X_LDO1_UV_STS 0x0001 /* LDO1_UV_STS */
+#define WM831X_LDO1_UV_STS_MASK 0x0001 /* LDO1_UV_STS */
+#define WM831X_LDO1_UV_STS_SHIFT 0 /* LDO1_UV_STS */
+#define WM831X_LDO1_UV_STS_WIDTH 1 /* LDO1_UV_STS */
+
+/*
+ * R16470 (0x4056) - DC1 Control 1
+ */
+#define WM831X_DC1_RATE_MASK 0xC000 /* DC1_RATE - [15:14] */
+#define WM831X_DC1_RATE_SHIFT 14 /* DC1_RATE - [15:14] */
+#define WM831X_DC1_RATE_WIDTH 2 /* DC1_RATE - [15:14] */
+#define WM831X_DC1_PHASE 0x1000 /* DC1_PHASE */
+#define WM831X_DC1_PHASE_MASK 0x1000 /* DC1_PHASE */
+#define WM831X_DC1_PHASE_SHIFT 12 /* DC1_PHASE */
+#define WM831X_DC1_PHASE_WIDTH 1 /* DC1_PHASE */
+#define WM831X_DC1_FREQ_MASK 0x0300 /* DC1_FREQ - [9:8] */
+#define WM831X_DC1_FREQ_SHIFT 8 /* DC1_FREQ - [9:8] */
+#define WM831X_DC1_FREQ_WIDTH 2 /* DC1_FREQ - [9:8] */
+#define WM831X_DC1_FLT 0x0080 /* DC1_FLT */
+#define WM831X_DC1_FLT_MASK 0x0080 /* DC1_FLT */
+#define WM831X_DC1_FLT_SHIFT 7 /* DC1_FLT */
+#define WM831X_DC1_FLT_WIDTH 1 /* DC1_FLT */
+#define WM831X_DC1_SOFT_START_MASK 0x0030 /* DC1_SOFT_START - [5:4] */
+#define WM831X_DC1_SOFT_START_SHIFT 4 /* DC1_SOFT_START - [5:4] */
+#define WM831X_DC1_SOFT_START_WIDTH 2 /* DC1_SOFT_START - [5:4] */
+#define WM831X_DC1_CAP_MASK 0x0003 /* DC1_CAP - [1:0] */
+#define WM831X_DC1_CAP_SHIFT 0 /* DC1_CAP - [1:0] */
+#define WM831X_DC1_CAP_WIDTH 2 /* DC1_CAP - [1:0] */
+
+/*
+ * R16471 (0x4057) - DC1 Control 2
+ */
+#define WM831X_DC1_ERR_ACT_MASK 0xC000 /* DC1_ERR_ACT - [15:14] */
+#define WM831X_DC1_ERR_ACT_SHIFT 14 /* DC1_ERR_ACT - [15:14] */
+#define WM831X_DC1_ERR_ACT_WIDTH 2 /* DC1_ERR_ACT - [15:14] */
+#define WM831X_DC1_HWC_SRC_MASK 0x1800 /* DC1_HWC_SRC - [12:11] */
+#define WM831X_DC1_HWC_SRC_SHIFT 11 /* DC1_HWC_SRC - [12:11] */
+#define WM831X_DC1_HWC_SRC_WIDTH 2 /* DC1_HWC_SRC - [12:11] */
+#define WM831X_DC1_HWC_VSEL 0x0400 /* DC1_HWC_VSEL */
+#define WM831X_DC1_HWC_VSEL_MASK 0x0400 /* DC1_HWC_VSEL */
+#define WM831X_DC1_HWC_VSEL_SHIFT 10 /* DC1_HWC_VSEL */
+#define WM831X_DC1_HWC_VSEL_WIDTH 1 /* DC1_HWC_VSEL */
+#define WM831X_DC1_HWC_MODE_MASK 0x0300 /* DC1_HWC_MODE - [9:8] */
+#define WM831X_DC1_HWC_MODE_SHIFT 8 /* DC1_HWC_MODE - [9:8] */
+#define WM831X_DC1_HWC_MODE_WIDTH 2 /* DC1_HWC_MODE - [9:8] */
+#define WM831X_DC1_HC_THR_MASK 0x0070 /* DC1_HC_THR - [6:4] */
+#define WM831X_DC1_HC_THR_SHIFT 4 /* DC1_HC_THR - [6:4] */
+#define WM831X_DC1_HC_THR_WIDTH 3 /* DC1_HC_THR - [6:4] */
+#define WM831X_DC1_HC_IND_ENA 0x0001 /* DC1_HC_IND_ENA */
+#define WM831X_DC1_HC_IND_ENA_MASK 0x0001 /* DC1_HC_IND_ENA */
+#define WM831X_DC1_HC_IND_ENA_SHIFT 0 /* DC1_HC_IND_ENA */
+#define WM831X_DC1_HC_IND_ENA_WIDTH 1 /* DC1_HC_IND_ENA */
+
+/*
+ * R16472 (0x4058) - DC1 ON Config
+ */
+#define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */
+#define WM831X_DC1_ON_SLOT_SHIFT 13 /* DC1_ON_SLOT - [15:13] */
+#define WM831X_DC1_ON_SLOT_WIDTH 3 /* DC1_ON_SLOT - [15:13] */
+#define WM831X_DC1_ON_MODE_MASK 0x0300 /* DC1_ON_MODE - [9:8] */
+#define WM831X_DC1_ON_MODE_SHIFT 8 /* DC1_ON_MODE - [9:8] */
+#define WM831X_DC1_ON_MODE_WIDTH 2 /* DC1_ON_MODE - [9:8] */
+#define WM831X_DC1_ON_VSEL_MASK 0x007F /* DC1_ON_VSEL - [6:0] */
+#define WM831X_DC1_ON_VSEL_SHIFT 0 /* DC1_ON_VSEL - [6:0] */
+#define WM831X_DC1_ON_VSEL_WIDTH 7 /* DC1_ON_VSEL - [6:0] */
+
+/*
+ * R16473 (0x4059) - DC1 SLEEP Control
+ */
+#define WM831X_DC1_SLP_SLOT_MASK 0xE000 /* DC1_SLP_SLOT - [15:13] */
+#define WM831X_DC1_SLP_SLOT_SHIFT 13 /* DC1_SLP_SLOT - [15:13] */
+#define WM831X_DC1_SLP_SLOT_WIDTH 3 /* DC1_SLP_SLOT - [15:13] */
+#define WM831X_DC1_SLP_MODE_MASK 0x0300 /* DC1_SLP_MODE - [9:8] */
+#define WM831X_DC1_SLP_MODE_SHIFT 8 /* DC1_SLP_MODE - [9:8] */
+#define WM831X_DC1_SLP_MODE_WIDTH 2 /* DC1_SLP_MODE - [9:8] */
+#define WM831X_DC1_SLP_VSEL_MASK 0x007F /* DC1_SLP_VSEL - [6:0] */
+#define WM831X_DC1_SLP_VSEL_SHIFT 0 /* DC1_SLP_VSEL - [6:0] */
+#define WM831X_DC1_SLP_VSEL_WIDTH 7 /* DC1_SLP_VSEL - [6:0] */
+
+/*
+ * R16474 (0x405A) - DC1 DVS Control
+ */
+#define WM831X_DC1_DVS_SRC_MASK 0x1800 /* DC1_DVS_SRC - [12:11] */
+#define WM831X_DC1_DVS_SRC_SHIFT 11 /* DC1_DVS_SRC - [12:11] */
+#define WM831X_DC1_DVS_SRC_WIDTH 2 /* DC1_DVS_SRC - [12:11] */
+#define WM831X_DC1_DVS_VSEL_MASK 0x007F /* DC1_DVS_VSEL - [6:0] */
+#define WM831X_DC1_DVS_VSEL_SHIFT 0 /* DC1_DVS_VSEL - [6:0] */
+#define WM831X_DC1_DVS_VSEL_WIDTH 7 /* DC1_DVS_VSEL - [6:0] */
+
+/*
+ * R16475 (0x405B) - DC2 Control 1
+ */
+#define WM831X_DC2_RATE_MASK 0xC000 /* DC2_RATE - [15:14] */
+#define WM831X_DC2_RATE_SHIFT 14 /* DC2_RATE - [15:14] */
+#define WM831X_DC2_RATE_WIDTH 2 /* DC2_RATE - [15:14] */
+#define WM831X_DC2_PHASE 0x1000 /* DC2_PHASE */
+#define WM831X_DC2_PHASE_MASK 0x1000 /* DC2_PHASE */
+#define WM831X_DC2_PHASE_SHIFT 12 /* DC2_PHASE */
+#define WM831X_DC2_PHASE_WIDTH 1 /* DC2_PHASE */
+#define WM831X_DC2_FREQ_MASK 0x0300 /* DC2_FREQ - [9:8] */
+#define WM831X_DC2_FREQ_SHIFT 8 /* DC2_FREQ - [9:8] */
+#define WM831X_DC2_FREQ_WIDTH 2 /* DC2_FREQ - [9:8] */
+#define WM831X_DC2_FLT 0x0080 /* DC2_FLT */
+#define WM831X_DC2_FLT_MASK 0x0080 /* DC2_FLT */
+#define WM831X_DC2_FLT_SHIFT 7 /* DC2_FLT */
+#define WM831X_DC2_FLT_WIDTH 1 /* DC2_FLT */
+#define WM831X_DC2_SOFT_START_MASK 0x0030 /* DC2_SOFT_START - [5:4] */
+#define WM831X_DC2_SOFT_START_SHIFT 4 /* DC2_SOFT_START - [5:4] */
+#define WM831X_DC2_SOFT_START_WIDTH 2 /* DC2_SOFT_START - [5:4] */
+#define WM831X_DC2_CAP_MASK 0x0003 /* DC2_CAP - [1:0] */
+#define WM831X_DC2_CAP_SHIFT 0 /* DC2_CAP - [1:0] */
+#define WM831X_DC2_CAP_WIDTH 2 /* DC2_CAP - [1:0] */
+
+/*
+ * R16476 (0x405C) - DC2 Control 2
+ */
+#define WM831X_DC2_ERR_ACT_MASK 0xC000 /* DC2_ERR_ACT - [15:14] */
+#define WM831X_DC2_ERR_ACT_SHIFT 14 /* DC2_ERR_ACT - [15:14] */
+#define WM831X_DC2_ERR_ACT_WIDTH 2 /* DC2_ERR_ACT - [15:14] */
+#define WM831X_DC2_HWC_SRC_MASK 0x1800 /* DC2_HWC_SRC - [12:11] */
+#define WM831X_DC2_HWC_SRC_SHIFT 11 /* DC2_HWC_SRC - [12:11] */
+#define WM831X_DC2_HWC_SRC_WIDTH 2 /* DC2_HWC_SRC - [12:11] */
+#define WM831X_DC2_HWC_VSEL 0x0400 /* DC2_HWC_VSEL */
+#define WM831X_DC2_HWC_VSEL_MASK 0x0400 /* DC2_HWC_VSEL */
+#define WM831X_DC2_HWC_VSEL_SHIFT 10 /* DC2_HWC_VSEL */
+#define WM831X_DC2_HWC_VSEL_WIDTH 1 /* DC2_HWC_VSEL */
+#define WM831X_DC2_HWC_MODE_MASK 0x0300 /* DC2_HWC_MODE - [9:8] */
+#define WM831X_DC2_HWC_MODE_SHIFT 8 /* DC2_HWC_MODE - [9:8] */
+#define WM831X_DC2_HWC_MODE_WIDTH 2 /* DC2_HWC_MODE - [9:8] */
+#define WM831X_DC2_HC_THR_MASK 0x0070 /* DC2_HC_THR - [6:4] */
+#define WM831X_DC2_HC_THR_SHIFT 4 /* DC2_HC_THR - [6:4] */
+#define WM831X_DC2_HC_THR_WIDTH 3 /* DC2_HC_THR - [6:4] */
+#define WM831X_DC2_HC_IND_ENA 0x0001 /* DC2_HC_IND_ENA */
+#define WM831X_DC2_HC_IND_ENA_MASK 0x0001 /* DC2_HC_IND_ENA */
+#define WM831X_DC2_HC_IND_ENA_SHIFT 0 /* DC2_HC_IND_ENA */
+#define WM831X_DC2_HC_IND_ENA_WIDTH 1 /* DC2_HC_IND_ENA */
+
+/*
+ * R16477 (0x405D) - DC2 ON Config
+ */
+#define WM831X_DC2_ON_SLOT_MASK 0xE000 /* DC2_ON_SLOT - [15:13] */
+#define WM831X_DC2_ON_SLOT_SHIFT 13 /* DC2_ON_SLOT - [15:13] */
+#define WM831X_DC2_ON_SLOT_WIDTH 3 /* DC2_ON_SLOT - [15:13] */
+#define WM831X_DC2_ON_MODE_MASK 0x0300 /* DC2_ON_MODE - [9:8] */
+#define WM831X_DC2_ON_MODE_SHIFT 8 /* DC2_ON_MODE - [9:8] */
+#define WM831X_DC2_ON_MODE_WIDTH 2 /* DC2_ON_MODE - [9:8] */
+#define WM831X_DC2_ON_VSEL_MASK 0x007F /* DC2_ON_VSEL - [6:0] */
+#define WM831X_DC2_ON_VSEL_SHIFT 0 /* DC2_ON_VSEL - [6:0] */
+#define WM831X_DC2_ON_VSEL_WIDTH 7 /* DC2_ON_VSEL - [6:0] */
+
+/*
+ * R16478 (0x405E) - DC2 SLEEP Control
+ */
+#define WM831X_DC2_SLP_SLOT_MASK 0xE000 /* DC2_SLP_SLOT - [15:13] */
+#define WM831X_DC2_SLP_SLOT_SHIFT 13 /* DC2_SLP_SLOT - [15:13] */
+#define WM831X_DC2_SLP_SLOT_WIDTH 3 /* DC2_SLP_SLOT - [15:13] */
+#define WM831X_DC2_SLP_MODE_MASK 0x0300 /* DC2_SLP_MODE - [9:8] */
+#define WM831X_DC2_SLP_MODE_SHIFT 8 /* DC2_SLP_MODE - [9:8] */
+#define WM831X_DC2_SLP_MODE_WIDTH 2 /* DC2_SLP_MODE - [9:8] */
+#define WM831X_DC2_SLP_VSEL_MASK 0x007F /* DC2_SLP_VSEL - [6:0] */
+#define WM831X_DC2_SLP_VSEL_SHIFT 0 /* DC2_SLP_VSEL - [6:0] */
+#define WM831X_DC2_SLP_VSEL_WIDTH 7 /* DC2_SLP_VSEL - [6:0] */
+
+/*
+ * R16479 (0x405F) - DC2 DVS Control
+ */
+#define WM831X_DC2_DVS_SRC_MASK 0x1800 /* DC2_DVS_SRC - [12:11] */
+#define WM831X_DC2_DVS_SRC_SHIFT 11 /* DC2_DVS_SRC - [12:11] */
+#define WM831X_DC2_DVS_SRC_WIDTH 2 /* DC2_DVS_SRC - [12:11] */
+#define WM831X_DC2_DVS_VSEL_MASK 0x007F /* DC2_DVS_VSEL - [6:0] */
+#define WM831X_DC2_DVS_VSEL_SHIFT 0 /* DC2_DVS_VSEL - [6:0] */
+#define WM831X_DC2_DVS_VSEL_WIDTH 7 /* DC2_DVS_VSEL - [6:0] */
+
+/*
+ * R16480 (0x4060) - DC3 Control 1
+ */
+#define WM831X_DC3_PHASE 0x1000 /* DC3_PHASE */
+#define WM831X_DC3_PHASE_MASK 0x1000 /* DC3_PHASE */
+#define WM831X_DC3_PHASE_SHIFT 12 /* DC3_PHASE */
+#define WM831X_DC3_PHASE_WIDTH 1 /* DC3_PHASE */
+#define WM831X_DC3_FLT 0x0080 /* DC3_FLT */
+#define WM831X_DC3_FLT_MASK 0x0080 /* DC3_FLT */
+#define WM831X_DC3_FLT_SHIFT 7 /* DC3_FLT */
+#define WM831X_DC3_FLT_WIDTH 1 /* DC3_FLT */
+#define WM831X_DC3_SOFT_START_MASK 0x0030 /* DC3_SOFT_START - [5:4] */
+#define WM831X_DC3_SOFT_START_SHIFT 4 /* DC3_SOFT_START - [5:4] */
+#define WM831X_DC3_SOFT_START_WIDTH 2 /* DC3_SOFT_START - [5:4] */
+#define WM831X_DC3_STNBY_LIM_MASK 0x000C /* DC3_STNBY_LIM - [3:2] */
+#define WM831X_DC3_STNBY_LIM_SHIFT 2 /* DC3_STNBY_LIM - [3:2] */
+#define WM831X_DC3_STNBY_LIM_WIDTH 2 /* DC3_STNBY_LIM - [3:2] */
+#define WM831X_DC3_CAP_MASK 0x0003 /* DC3_CAP - [1:0] */
+#define WM831X_DC3_CAP_SHIFT 0 /* DC3_CAP - [1:0] */
+#define WM831X_DC3_CAP_WIDTH 2 /* DC3_CAP - [1:0] */
+
+/*
+ * R16481 (0x4061) - DC3 Control 2
+ */
+#define WM831X_DC3_ERR_ACT_MASK 0xC000 /* DC3_ERR_ACT - [15:14] */
+#define WM831X_DC3_ERR_ACT_SHIFT 14 /* DC3_ERR_ACT - [15:14] */
+#define WM831X_DC3_ERR_ACT_WIDTH 2 /* DC3_ERR_ACT - [15:14] */
+#define WM831X_DC3_HWC_SRC_MASK 0x1800 /* DC3_HWC_SRC - [12:11] */
+#define WM831X_DC3_HWC_SRC_SHIFT 11 /* DC3_HWC_SRC - [12:11] */
+#define WM831X_DC3_HWC_SRC_WIDTH 2 /* DC3_HWC_SRC - [12:11] */
+#define WM831X_DC3_HWC_VSEL 0x0400 /* DC3_HWC_VSEL */
+#define WM831X_DC3_HWC_VSEL_MASK 0x0400 /* DC3_HWC_VSEL */
+#define WM831X_DC3_HWC_VSEL_SHIFT 10 /* DC3_HWC_VSEL */
+#define WM831X_DC3_HWC_VSEL_WIDTH 1 /* DC3_HWC_VSEL */
+#define WM831X_DC3_HWC_MODE_MASK 0x0300 /* DC3_HWC_MODE - [9:8] */
+#define WM831X_DC3_HWC_MODE_SHIFT 8 /* DC3_HWC_MODE - [9:8] */
+#define WM831X_DC3_HWC_MODE_WIDTH 2 /* DC3_HWC_MODE - [9:8] */
+#define WM831X_DC3_OVP 0x0080 /* DC3_OVP */
+#define WM831X_DC3_OVP_MASK 0x0080 /* DC3_OVP */
+#define WM831X_DC3_OVP_SHIFT 7 /* DC3_OVP */
+#define WM831X_DC3_OVP_WIDTH 1 /* DC3_OVP */
+
+/*
+ * R16482 (0x4062) - DC3 ON Config
+ */
+#define WM831X_DC3_ON_SLOT_MASK 0xE000 /* DC3_ON_SLOT - [15:13] */
+#define WM831X_DC3_ON_SLOT_SHIFT 13 /* DC3_ON_SLOT - [15:13] */
+#define WM831X_DC3_ON_SLOT_WIDTH 3 /* DC3_ON_SLOT - [15:13] */
+#define WM831X_DC3_ON_MODE_MASK 0x0300 /* DC3_ON_MODE - [9:8] */
+#define WM831X_DC3_ON_MODE_SHIFT 8 /* DC3_ON_MODE - [9:8] */
+#define WM831X_DC3_ON_MODE_WIDTH 2 /* DC3_ON_MODE - [9:8] */
+#define WM831X_DC3_ON_VSEL_MASK 0x007F /* DC3_ON_VSEL - [6:0] */
+#define WM831X_DC3_ON_VSEL_SHIFT 0 /* DC3_ON_VSEL - [6:0] */
+#define WM831X_DC3_ON_VSEL_WIDTH 7 /* DC3_ON_VSEL - [6:0] */
+
+/*
+ * R16483 (0x4063) - DC3 SLEEP Control
+ */
+#define WM831X_DC3_SLP_SLOT_MASK 0xE000 /* DC3_SLP_SLOT - [15:13] */
+#define WM831X_DC3_SLP_SLOT_SHIFT 13 /* DC3_SLP_SLOT - [15:13] */
+#define WM831X_DC3_SLP_SLOT_WIDTH 3 /* DC3_SLP_SLOT - [15:13] */
+#define WM831X_DC3_SLP_MODE_MASK 0x0300 /* DC3_SLP_MODE - [9:8] */
+#define WM831X_DC3_SLP_MODE_SHIFT 8 /* DC3_SLP_MODE - [9:8] */
+#define WM831X_DC3_SLP_MODE_WIDTH 2 /* DC3_SLP_MODE - [9:8] */
+#define WM831X_DC3_SLP_VSEL_MASK 0x007F /* DC3_SLP_VSEL - [6:0] */
+#define WM831X_DC3_SLP_VSEL_SHIFT 0 /* DC3_SLP_VSEL - [6:0] */
+#define WM831X_DC3_SLP_VSEL_WIDTH 7 /* DC3_SLP_VSEL - [6:0] */
+
+/*
+ * R16484 (0x4064) - DC4 Control
+ */
+#define WM831X_DC4_ERR_ACT_MASK 0xC000 /* DC4_ERR_ACT - [15:14] */
+#define WM831X_DC4_ERR_ACT_SHIFT 14 /* DC4_ERR_ACT - [15:14] */
+#define WM831X_DC4_ERR_ACT_WIDTH 2 /* DC4_ERR_ACT - [15:14] */
+#define WM831X_DC4_HWC_SRC_MASK 0x1800 /* DC4_HWC_SRC - [12:11] */
+#define WM831X_DC4_HWC_SRC_SHIFT 11 /* DC4_HWC_SRC - [12:11] */
+#define WM831X_DC4_HWC_SRC_WIDTH 2 /* DC4_HWC_SRC - [12:11] */
+#define WM831X_DC4_HWC_MODE 0x0100 /* DC4_HWC_MODE */
+#define WM831X_DC4_HWC_MODE_MASK 0x0100 /* DC4_HWC_MODE */
+#define WM831X_DC4_HWC_MODE_SHIFT 8 /* DC4_HWC_MODE */
+#define WM831X_DC4_HWC_MODE_WIDTH 1 /* DC4_HWC_MODE */
+#define WM831X_DC4_RANGE_MASK 0x000C /* DC4_RANGE - [3:2] */
+#define WM831X_DC4_RANGE_SHIFT 2 /* DC4_RANGE - [3:2] */
+#define WM831X_DC4_RANGE_WIDTH 2 /* DC4_RANGE - [3:2] */
+#define WM831X_DC4_FBSRC 0x0001 /* DC4_FBSRC */
+#define WM831X_DC4_FBSRC_MASK 0x0001 /* DC4_FBSRC */
+#define WM831X_DC4_FBSRC_SHIFT 0 /* DC4_FBSRC */
+#define WM831X_DC4_FBSRC_WIDTH 1 /* DC4_FBSRC */
+
+/*
+ * R16485 (0x4065) - DC4 SLEEP Control
+ */
+#define WM831X_DC4_SLPENA 0x0100 /* DC4_SLPENA */
+#define WM831X_DC4_SLPENA_MASK 0x0100 /* DC4_SLPENA */
+#define WM831X_DC4_SLPENA_SHIFT 8 /* DC4_SLPENA */
+#define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */
+
+/*
+ * R16488 (0x4068) - LDO1 Control
+ */
+#define WM831X_LDO1_ERR_ACT_MASK 0xC000 /* LDO1_ERR_ACT - [15:14] */
+#define WM831X_LDO1_ERR_ACT_SHIFT 14 /* LDO1_ERR_ACT - [15:14] */
+#define WM831X_LDO1_ERR_ACT_WIDTH 2 /* LDO1_ERR_ACT - [15:14] */
+#define WM831X_LDO1_HWC_SRC_MASK 0x1800 /* LDO1_HWC_SRC - [12:11] */
+#define WM831X_LDO1_HWC_SRC_SHIFT 11 /* LDO1_HWC_SRC - [12:11] */
+#define WM831X_LDO1_HWC_SRC_WIDTH 2 /* LDO1_HWC_SRC - [12:11] */
+#define WM831X_LDO1_HWC_VSEL 0x0400 /* LDO1_HWC_VSEL */
+#define WM831X_LDO1_HWC_VSEL_MASK 0x0400 /* LDO1_HWC_VSEL */
+#define WM831X_LDO1_HWC_VSEL_SHIFT 10 /* LDO1_HWC_VSEL */
+#define WM831X_LDO1_HWC_VSEL_WIDTH 1 /* LDO1_HWC_VSEL */
+#define WM831X_LDO1_HWC_MODE_MASK 0x0300 /* LDO1_HWC_MODE - [9:8] */
+#define WM831X_LDO1_HWC_MODE_SHIFT 8 /* LDO1_HWC_MODE - [9:8] */
+#define WM831X_LDO1_HWC_MODE_WIDTH 2 /* LDO1_HWC_MODE - [9:8] */
+#define WM831X_LDO1_FLT 0x0080 /* LDO1_FLT */
+#define WM831X_LDO1_FLT_MASK 0x0080 /* LDO1_FLT */
+#define WM831X_LDO1_FLT_SHIFT 7 /* LDO1_FLT */
+#define WM831X_LDO1_FLT_WIDTH 1 /* LDO1_FLT */
+#define WM831X_LDO1_SWI 0x0040 /* LDO1_SWI */
+#define WM831X_LDO1_SWI_MASK 0x0040 /* LDO1_SWI */
+#define WM831X_LDO1_SWI_SHIFT 6 /* LDO1_SWI */
+#define WM831X_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
+#define WM831X_LDO1_LP_MODE 0x0001 /* LDO1_LP_MODE */
+#define WM831X_LDO1_LP_MODE_MASK 0x0001 /* LDO1_LP_MODE */
+#define WM831X_LDO1_LP_MODE_SHIFT 0 /* LDO1_LP_MODE */
+#define WM831X_LDO1_LP_MODE_WIDTH 1 /* LDO1_LP_MODE */
+
+/*
+ * R16489 (0x4069) - LDO1 ON Control
+ */
+#define WM831X_LDO1_ON_SLOT_MASK 0xE000 /* LDO1_ON_SLOT - [15:13] */
+#define WM831X_LDO1_ON_SLOT_SHIFT 13 /* LDO1_ON_SLOT - [15:13] */
+#define WM831X_LDO1_ON_SLOT_WIDTH 3 /* LDO1_ON_SLOT - [15:13] */
+#define WM831X_LDO1_ON_MODE 0x0100 /* LDO1_ON_MODE */
+#define WM831X_LDO1_ON_MODE_MASK 0x0100 /* LDO1_ON_MODE */
+#define WM831X_LDO1_ON_MODE_SHIFT 8 /* LDO1_ON_MODE */
+#define WM831X_LDO1_ON_MODE_WIDTH 1 /* LDO1_ON_MODE */
+#define WM831X_LDO1_ON_VSEL_MASK 0x001F /* LDO1_ON_VSEL - [4:0] */
+#define WM831X_LDO1_ON_VSEL_SHIFT 0 /* LDO1_ON_VSEL - [4:0] */
+#define WM831X_LDO1_ON_VSEL_WIDTH 5 /* LDO1_ON_VSEL - [4:0] */
+
+/*
+ * R16490 (0x406A) - LDO1 SLEEP Control
+ */
+#define WM831X_LDO1_SLP_SLOT_MASK 0xE000 /* LDO1_SLP_SLOT - [15:13] */
+#define WM831X_LDO1_SLP_SLOT_SHIFT 13 /* LDO1_SLP_SLOT - [15:13] */
+#define WM831X_LDO1_SLP_SLOT_WIDTH 3 /* LDO1_SLP_SLOT - [15:13] */
+#define WM831X_LDO1_SLP_MODE 0x0100 /* LDO1_SLP_MODE */
+#define WM831X_LDO1_SLP_MODE_MASK 0x0100 /* LDO1_SLP_MODE */
+#define WM831X_LDO1_SLP_MODE_SHIFT 8 /* LDO1_SLP_MODE */
+#define WM831X_LDO1_SLP_MODE_WIDTH 1 /* LDO1_SLP_MODE */
+#define WM831X_LDO1_SLP_VSEL_MASK 0x001F /* LDO1_SLP_VSEL - [4:0] */
+#define WM831X_LDO1_SLP_VSEL_SHIFT 0 /* LDO1_SLP_VSEL - [4:0] */
+#define WM831X_LDO1_SLP_VSEL_WIDTH 5 /* LDO1_SLP_VSEL - [4:0] */
+
+/*
+ * R16491 (0x406B) - LDO2 Control
+ */
+#define WM831X_LDO2_ERR_ACT_MASK 0xC000 /* LDO2_ERR_ACT - [15:14] */
+#define WM831X_LDO2_ERR_ACT_SHIFT 14 /* LDO2_ERR_ACT - [15:14] */
+#define WM831X_LDO2_ERR_ACT_WIDTH 2 /* LDO2_ERR_ACT - [15:14] */
+#define WM831X_LDO2_HWC_SRC_MASK 0x1800 /* LDO2_HWC_SRC - [12:11] */
+#define WM831X_LDO2_HWC_SRC_SHIFT 11 /* LDO2_HWC_SRC - [12:11] */
+#define WM831X_LDO2_HWC_SRC_WIDTH 2 /* LDO2_HWC_SRC - [12:11] */
+#define WM831X_LDO2_HWC_VSEL 0x0400 /* LDO2_HWC_VSEL */
+#define WM831X_LDO2_HWC_VSEL_MASK 0x0400 /* LDO2_HWC_VSEL */
+#define WM831X_LDO2_HWC_VSEL_SHIFT 10 /* LDO2_HWC_VSEL */
+#define WM831X_LDO2_HWC_VSEL_WIDTH 1 /* LDO2_HWC_VSEL */
+#define WM831X_LDO2_HWC_MODE_MASK 0x0300 /* LDO2_HWC_MODE - [9:8] */
+#define WM831X_LDO2_HWC_MODE_SHIFT 8 /* LDO2_HWC_MODE - [9:8] */
+#define WM831X_LDO2_HWC_MODE_WIDTH 2 /* LDO2_HWC_MODE - [9:8] */
+#define WM831X_LDO2_FLT 0x0080 /* LDO2_FLT */
+#define WM831X_LDO2_FLT_MASK 0x0080 /* LDO2_FLT */
+#define WM831X_LDO2_FLT_SHIFT 7 /* LDO2_FLT */
+#define WM831X_LDO2_FLT_WIDTH 1 /* LDO2_FLT */
+#define WM831X_LDO2_SWI 0x0040 /* LDO2_SWI */
+#define WM831X_LDO2_SWI_MASK 0x0040 /* LDO2_SWI */
+#define WM831X_LDO2_SWI_SHIFT 6 /* LDO2_SWI */
+#define WM831X_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
+#define WM831X_LDO2_LP_MODE 0x0001 /* LDO2_LP_MODE */
+#define WM831X_LDO2_LP_MODE_MASK 0x0001 /* LDO2_LP_MODE */
+#define WM831X_LDO2_LP_MODE_SHIFT 0 /* LDO2_LP_MODE */
+#define WM831X_LDO2_LP_MODE_WIDTH 1 /* LDO2_LP_MODE */
+
+/*
+ * R16492 (0x406C) - LDO2 ON Control
+ */
+#define WM831X_LDO2_ON_SLOT_MASK 0xE000 /* LDO2_ON_SLOT - [15:13] */
+#define WM831X_LDO2_ON_SLOT_SHIFT 13 /* LDO2_ON_SLOT - [15:13] */
+#define WM831X_LDO2_ON_SLOT_WIDTH 3 /* LDO2_ON_SLOT - [15:13] */
+#define WM831X_LDO2_ON_MODE 0x0100 /* LDO2_ON_MODE */
+#define WM831X_LDO2_ON_MODE_MASK 0x0100 /* LDO2_ON_MODE */
+#define WM831X_LDO2_ON_MODE_SHIFT 8 /* LDO2_ON_MODE */
+#define WM831X_LDO2_ON_MODE_WIDTH 1 /* LDO2_ON_MODE */
+#define WM831X_LDO2_ON_VSEL_MASK 0x001F /* LDO2_ON_VSEL - [4:0] */
+#define WM831X_LDO2_ON_VSEL_SHIFT 0 /* LDO2_ON_VSEL - [4:0] */
+#define WM831X_LDO2_ON_VSEL_WIDTH 5 /* LDO2_ON_VSEL - [4:0] */
+
+/*
+ * R16493 (0x406D) - LDO2 SLEEP Control
+ */
+#define WM831X_LDO2_SLP_SLOT_MASK 0xE000 /* LDO2_SLP_SLOT - [15:13] */
+#define WM831X_LDO2_SLP_SLOT_SHIFT 13 /* LDO2_SLP_SLOT - [15:13] */
+#define WM831X_LDO2_SLP_SLOT_WIDTH 3 /* LDO2_SLP_SLOT - [15:13] */
+#define WM831X_LDO2_SLP_MODE 0x0100 /* LDO2_SLP_MODE */
+#define WM831X_LDO2_SLP_MODE_MASK 0x0100 /* LDO2_SLP_MODE */
+#define WM831X_LDO2_SLP_MODE_SHIFT 8 /* LDO2_SLP_MODE */
+#define WM831X_LDO2_SLP_MODE_WIDTH 1 /* LDO2_SLP_MODE */
+#define WM831X_LDO2_SLP_VSEL_MASK 0x001F /* LDO2_SLP_VSEL - [4:0] */
+#define WM831X_LDO2_SLP_VSEL_SHIFT 0 /* LDO2_SLP_VSEL - [4:0] */
+#define WM831X_LDO2_SLP_VSEL_WIDTH 5 /* LDO2_SLP_VSEL - [4:0] */
+
+/*
+ * R16494 (0x406E) - LDO3 Control
+ */
+#define WM831X_LDO3_ERR_ACT_MASK 0xC000 /* LDO3_ERR_ACT - [15:14] */
+#define WM831X_LDO3_ERR_ACT_SHIFT 14 /* LDO3_ERR_ACT - [15:14] */
+#define WM831X_LDO3_ERR_ACT_WIDTH 2 /* LDO3_ERR_ACT - [15:14] */
+#define WM831X_LDO3_HWC_SRC_MASK 0x1800 /* LDO3_HWC_SRC - [12:11] */
+#define WM831X_LDO3_HWC_SRC_SHIFT 11 /* LDO3_HWC_SRC - [12:11] */
+#define WM831X_LDO3_HWC_SRC_WIDTH 2 /* LDO3_HWC_SRC - [12:11] */
+#define WM831X_LDO3_HWC_VSEL 0x0400 /* LDO3_HWC_VSEL */
+#define WM831X_LDO3_HWC_VSEL_MASK 0x0400 /* LDO3_HWC_VSEL */
+#define WM831X_LDO3_HWC_VSEL_SHIFT 10 /* LDO3_HWC_VSEL */
+#define WM831X_LDO3_HWC_VSEL_WIDTH 1 /* LDO3_HWC_VSEL */
+#define WM831X_LDO3_HWC_MODE_MASK 0x0300 /* LDO3_HWC_MODE - [9:8] */
+#define WM831X_LDO3_HWC_MODE_SHIFT 8 /* LDO3_HWC_MODE - [9:8] */
+#define WM831X_LDO3_HWC_MODE_WIDTH 2 /* LDO3_HWC_MODE - [9:8] */
+#define WM831X_LDO3_FLT 0x0080 /* LDO3_FLT */
+#define WM831X_LDO3_FLT_MASK 0x0080 /* LDO3_FLT */
+#define WM831X_LDO3_FLT_SHIFT 7 /* LDO3_FLT */
+#define WM831X_LDO3_FLT_WIDTH 1 /* LDO3_FLT */
+#define WM831X_LDO3_SWI 0x0040 /* LDO3_SWI */
+#define WM831X_LDO3_SWI_MASK 0x0040 /* LDO3_SWI */
+#define WM831X_LDO3_SWI_SHIFT 6 /* LDO3_SWI */
+#define WM831X_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
+#define WM831X_LDO3_LP_MODE 0x0001 /* LDO3_LP_MODE */
+#define WM831X_LDO3_LP_MODE_MASK 0x0001 /* LDO3_LP_MODE */
+#define WM831X_LDO3_LP_MODE_SHIFT 0 /* LDO3_LP_MODE */
+#define WM831X_LDO3_LP_MODE_WIDTH 1 /* LDO3_LP_MODE */
+
+/*
+ * R16495 (0x406F) - LDO3 ON Control
+ */
+#define WM831X_LDO3_ON_SLOT_MASK 0xE000 /* LDO3_ON_SLOT - [15:13] */
+#define WM831X_LDO3_ON_SLOT_SHIFT 13 /* LDO3_ON_SLOT - [15:13] */
+#define WM831X_LDO3_ON_SLOT_WIDTH 3 /* LDO3_ON_SLOT - [15:13] */
+#define WM831X_LDO3_ON_MODE 0x0100 /* LDO3_ON_MODE */
+#define WM831X_LDO3_ON_MODE_MASK 0x0100 /* LDO3_ON_MODE */
+#define WM831X_LDO3_ON_MODE_SHIFT 8 /* LDO3_ON_MODE */
+#define WM831X_LDO3_ON_MODE_WIDTH 1 /* LDO3_ON_MODE */
+#define WM831X_LDO3_ON_VSEL_MASK 0x001F /* LDO3_ON_VSEL - [4:0] */
+#define WM831X_LDO3_ON_VSEL_SHIFT 0 /* LDO3_ON_VSEL - [4:0] */
+#define WM831X_LDO3_ON_VSEL_WIDTH 5 /* LDO3_ON_VSEL - [4:0] */
+
+/*
+ * R16496 (0x4070) - LDO3 SLEEP Control
+ */
+#define WM831X_LDO3_SLP_SLOT_MASK 0xE000 /* LDO3_SLP_SLOT - [15:13] */
+#define WM831X_LDO3_SLP_SLOT_SHIFT 13 /* LDO3_SLP_SLOT - [15:13] */
+#define WM831X_LDO3_SLP_SLOT_WIDTH 3 /* LDO3_SLP_SLOT - [15:13] */
+#define WM831X_LDO3_SLP_MODE 0x0100 /* LDO3_SLP_MODE */
+#define WM831X_LDO3_SLP_MODE_MASK 0x0100 /* LDO3_SLP_MODE */
+#define WM831X_LDO3_SLP_MODE_SHIFT 8 /* LDO3_SLP_MODE */
+#define WM831X_LDO3_SLP_MODE_WIDTH 1 /* LDO3_SLP_MODE */
+#define WM831X_LDO3_SLP_VSEL_MASK 0x001F /* LDO3_SLP_VSEL - [4:0] */
+#define WM831X_LDO3_SLP_VSEL_SHIFT 0 /* LDO3_SLP_VSEL - [4:0] */
+#define WM831X_LDO3_SLP_VSEL_WIDTH 5 /* LDO3_SLP_VSEL - [4:0] */
+
+/*
+ * R16497 (0x4071) - LDO4 Control
+ */
+#define WM831X_LDO4_ERR_ACT_MASK 0xC000 /* LDO4_ERR_ACT - [15:14] */
+#define WM831X_LDO4_ERR_ACT_SHIFT 14 /* LDO4_ERR_ACT - [15:14] */
+#define WM831X_LDO4_ERR_ACT_WIDTH 2 /* LDO4_ERR_ACT - [15:14] */
+#define WM831X_LDO4_HWC_SRC_MASK 0x1800 /* LDO4_HWC_SRC - [12:11] */
+#define WM831X_LDO4_HWC_SRC_SHIFT 11 /* LDO4_HWC_SRC - [12:11] */
+#define WM831X_LDO4_HWC_SRC_WIDTH 2 /* LDO4_HWC_SRC - [12:11] */
+#define WM831X_LDO4_HWC_VSEL 0x0400 /* LDO4_HWC_VSEL */
+#define WM831X_LDO4_HWC_VSEL_MASK 0x0400 /* LDO4_HWC_VSEL */
+#define WM831X_LDO4_HWC_VSEL_SHIFT 10 /* LDO4_HWC_VSEL */
+#define WM831X_LDO4_HWC_VSEL_WIDTH 1 /* LDO4_HWC_VSEL */
+#define WM831X_LDO4_HWC_MODE_MASK 0x0300 /* LDO4_HWC_MODE - [9:8] */
+#define WM831X_LDO4_HWC_MODE_SHIFT 8 /* LDO4_HWC_MODE - [9:8] */
+#define WM831X_LDO4_HWC_MODE_WIDTH 2 /* LDO4_HWC_MODE - [9:8] */
+#define WM831X_LDO4_FLT 0x0080 /* LDO4_FLT */
+#define WM831X_LDO4_FLT_MASK 0x0080 /* LDO4_FLT */
+#define WM831X_LDO4_FLT_SHIFT 7 /* LDO4_FLT */
+#define WM831X_LDO4_FLT_WIDTH 1 /* LDO4_FLT */
+#define WM831X_LDO4_SWI 0x0040 /* LDO4_SWI */
+#define WM831X_LDO4_SWI_MASK 0x0040 /* LDO4_SWI */
+#define WM831X_LDO4_SWI_SHIFT 6 /* LDO4_SWI */
+#define WM831X_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
+#define WM831X_LDO4_LP_MODE 0x0001 /* LDO4_LP_MODE */
+#define WM831X_LDO4_LP_MODE_MASK 0x0001 /* LDO4_LP_MODE */
+#define WM831X_LDO4_LP_MODE_SHIFT 0 /* LDO4_LP_MODE */
+#define WM831X_LDO4_LP_MODE_WIDTH 1 /* LDO4_LP_MODE */
+
+/*
+ * R16498 (0x4072) - LDO4 ON Control
+ */
+#define WM831X_LDO4_ON_SLOT_MASK 0xE000 /* LDO4_ON_SLOT - [15:13] */
+#define WM831X_LDO4_ON_SLOT_SHIFT 13 /* LDO4_ON_SLOT - [15:13] */
+#define WM831X_LDO4_ON_SLOT_WIDTH 3 /* LDO4_ON_SLOT - [15:13] */
+#define WM831X_LDO4_ON_MODE 0x0100 /* LDO4_ON_MODE */
+#define WM831X_LDO4_ON_MODE_MASK 0x0100 /* LDO4_ON_MODE */
+#define WM831X_LDO4_ON_MODE_SHIFT 8 /* LDO4_ON_MODE */
+#define WM831X_LDO4_ON_MODE_WIDTH 1 /* LDO4_ON_MODE */
+#define WM831X_LDO4_ON_VSEL_MASK 0x001F /* LDO4_ON_VSEL - [4:0] */
+#define WM831X_LDO4_ON_VSEL_SHIFT 0 /* LDO4_ON_VSEL - [4:0] */
+#define WM831X_LDO4_ON_VSEL_WIDTH 5 /* LDO4_ON_VSEL - [4:0] */
+
+/*
+ * R16499 (0x4073) - LDO4 SLEEP Control
+ */
+#define WM831X_LDO4_SLP_SLOT_MASK 0xE000 /* LDO4_SLP_SLOT - [15:13] */
+#define WM831X_LDO4_SLP_SLOT_SHIFT 13 /* LDO4_SLP_SLOT - [15:13] */
+#define WM831X_LDO4_SLP_SLOT_WIDTH 3 /* LDO4_SLP_SLOT - [15:13] */
+#define WM831X_LDO4_SLP_MODE 0x0100 /* LDO4_SLP_MODE */
+#define WM831X_LDO4_SLP_MODE_MASK 0x0100 /* LDO4_SLP_MODE */
+#define WM831X_LDO4_SLP_MODE_SHIFT 8 /* LDO4_SLP_MODE */
+#define WM831X_LDO4_SLP_MODE_WIDTH 1 /* LDO4_SLP_MODE */
+#define WM831X_LDO4_SLP_VSEL_MASK 0x001F /* LDO4_SLP_VSEL - [4:0] */
+#define WM831X_LDO4_SLP_VSEL_SHIFT 0 /* LDO4_SLP_VSEL - [4:0] */
+#define WM831X_LDO4_SLP_VSEL_WIDTH 5 /* LDO4_SLP_VSEL - [4:0] */
+
+/*
+ * R16500 (0x4074) - LDO5 Control
+ */
+#define WM831X_LDO5_ERR_ACT_MASK 0xC000 /* LDO5_ERR_ACT - [15:14] */
+#define WM831X_LDO5_ERR_ACT_SHIFT 14 /* LDO5_ERR_ACT - [15:14] */
+#define WM831X_LDO5_ERR_ACT_WIDTH 2 /* LDO5_ERR_ACT - [15:14] */
+#define WM831X_LDO5_HWC_SRC_MASK 0x1800 /* LDO5_HWC_SRC - [12:11] */
+#define WM831X_LDO5_HWC_SRC_SHIFT 11 /* LDO5_HWC_SRC - [12:11] */
+#define WM831X_LDO5_HWC_SRC_WIDTH 2 /* LDO5_HWC_SRC - [12:11] */
+#define WM831X_LDO5_HWC_VSEL 0x0400 /* LDO5_HWC_VSEL */
+#define WM831X_LDO5_HWC_VSEL_MASK 0x0400 /* LDO5_HWC_VSEL */
+#define WM831X_LDO5_HWC_VSEL_SHIFT 10 /* LDO5_HWC_VSEL */
+#define WM831X_LDO5_HWC_VSEL_WIDTH 1 /* LDO5_HWC_VSEL */
+#define WM831X_LDO5_HWC_MODE_MASK 0x0300 /* LDO5_HWC_MODE - [9:8] */
+#define WM831X_LDO5_HWC_MODE_SHIFT 8 /* LDO5_HWC_MODE - [9:8] */
+#define WM831X_LDO5_HWC_MODE_WIDTH 2 /* LDO5_HWC_MODE - [9:8] */
+#define WM831X_LDO5_FLT 0x0080 /* LDO5_FLT */
+#define WM831X_LDO5_FLT_MASK 0x0080 /* LDO5_FLT */
+#define WM831X_LDO5_FLT_SHIFT 7 /* LDO5_FLT */
+#define WM831X_LDO5_FLT_WIDTH 1 /* LDO5_FLT */
+#define WM831X_LDO5_SWI 0x0040 /* LDO5_SWI */
+#define WM831X_LDO5_SWI_MASK 0x0040 /* LDO5_SWI */
+#define WM831X_LDO5_SWI_SHIFT 6 /* LDO5_SWI */
+#define WM831X_LDO5_SWI_WIDTH 1 /* LDO5_SWI */
+#define WM831X_LDO5_LP_MODE 0x0001 /* LDO5_LP_MODE */
+#define WM831X_LDO5_LP_MODE_MASK 0x0001 /* LDO5_LP_MODE */
+#define WM831X_LDO5_LP_MODE_SHIFT 0 /* LDO5_LP_MODE */
+#define WM831X_LDO5_LP_MODE_WIDTH 1 /* LDO5_LP_MODE */
+
+/*
+ * R16501 (0x4075) - LDO5 ON Control
+ */
+#define WM831X_LDO5_ON_SLOT_MASK 0xE000 /* LDO5_ON_SLOT - [15:13] */
+#define WM831X_LDO5_ON_SLOT_SHIFT 13 /* LDO5_ON_SLOT - [15:13] */
+#define WM831X_LDO5_ON_SLOT_WIDTH 3 /* LDO5_ON_SLOT - [15:13] */
+#define WM831X_LDO5_ON_MODE 0x0100 /* LDO5_ON_MODE */
+#define WM831X_LDO5_ON_MODE_MASK 0x0100 /* LDO5_ON_MODE */
+#define WM831X_LDO5_ON_MODE_SHIFT 8 /* LDO5_ON_MODE */
+#define WM831X_LDO5_ON_MODE_WIDTH 1 /* LDO5_ON_MODE */
+#define WM831X_LDO5_ON_VSEL_MASK 0x001F /* LDO5_ON_VSEL - [4:0] */
+#define WM831X_LDO5_ON_VSEL_SHIFT 0 /* LDO5_ON_VSEL - [4:0] */
+#define WM831X_LDO5_ON_VSEL_WIDTH 5 /* LDO5_ON_VSEL - [4:0] */
+
+/*
+ * R16502 (0x4076) - LDO5 SLEEP Control
+ */
+#define WM831X_LDO5_SLP_SLOT_MASK 0xE000 /* LDO5_SLP_SLOT - [15:13] */
+#define WM831X_LDO5_SLP_SLOT_SHIFT 13 /* LDO5_SLP_SLOT - [15:13] */
+#define WM831X_LDO5_SLP_SLOT_WIDTH 3 /* LDO5_SLP_SLOT - [15:13] */
+#define WM831X_LDO5_SLP_MODE 0x0100 /* LDO5_SLP_MODE */
+#define WM831X_LDO5_SLP_MODE_MASK 0x0100 /* LDO5_SLP_MODE */
+#define WM831X_LDO5_SLP_MODE_SHIFT 8 /* LDO5_SLP_MODE */
+#define WM831X_LDO5_SLP_MODE_WIDTH 1 /* LDO5_SLP_MODE */
+#define WM831X_LDO5_SLP_VSEL_MASK 0x001F /* LDO5_SLP_VSEL - [4:0] */
+#define WM831X_LDO5_SLP_VSEL_SHIFT 0 /* LDO5_SLP_VSEL - [4:0] */
+#define WM831X_LDO5_SLP_VSEL_WIDTH 5 /* LDO5_SLP_VSEL - [4:0] */
+
+/*
+ * R16503 (0x4077) - LDO6 Control
+ */
+#define WM831X_LDO6_ERR_ACT_MASK 0xC000 /* LDO6_ERR_ACT - [15:14] */
+#define WM831X_LDO6_ERR_ACT_SHIFT 14 /* LDO6_ERR_ACT - [15:14] */
+#define WM831X_LDO6_ERR_ACT_WIDTH 2 /* LDO6_ERR_ACT - [15:14] */
+#define WM831X_LDO6_HWC_SRC_MASK 0x1800 /* LDO6_HWC_SRC - [12:11] */
+#define WM831X_LDO6_HWC_SRC_SHIFT 11 /* LDO6_HWC_SRC - [12:11] */
+#define WM831X_LDO6_HWC_SRC_WIDTH 2 /* LDO6_HWC_SRC - [12:11] */
+#define WM831X_LDO6_HWC_VSEL 0x0400 /* LDO6_HWC_VSEL */
+#define WM831X_LDO6_HWC_VSEL_MASK 0x0400 /* LDO6_HWC_VSEL */
+#define WM831X_LDO6_HWC_VSEL_SHIFT 10 /* LDO6_HWC_VSEL */
+#define WM831X_LDO6_HWC_VSEL_WIDTH 1 /* LDO6_HWC_VSEL */
+#define WM831X_LDO6_HWC_MODE_MASK 0x0300 /* LDO6_HWC_MODE - [9:8] */
+#define WM831X_LDO6_HWC_MODE_SHIFT 8 /* LDO6_HWC_MODE - [9:8] */
+#define WM831X_LDO6_HWC_MODE_WIDTH 2 /* LDO6_HWC_MODE - [9:8] */
+#define WM831X_LDO6_FLT 0x0080 /* LDO6_FLT */
+#define WM831X_LDO6_FLT_MASK 0x0080 /* LDO6_FLT */
+#define WM831X_LDO6_FLT_SHIFT 7 /* LDO6_FLT */
+#define WM831X_LDO6_FLT_WIDTH 1 /* LDO6_FLT */
+#define WM831X_LDO6_SWI 0x0040 /* LDO6_SWI */
+#define WM831X_LDO6_SWI_MASK 0x0040 /* LDO6_SWI */
+#define WM831X_LDO6_SWI_SHIFT 6 /* LDO6_SWI */
+#define WM831X_LDO6_SWI_WIDTH 1 /* LDO6_SWI */
+#define WM831X_LDO6_LP_MODE 0x0001 /* LDO6_LP_MODE */
+#define WM831X_LDO6_LP_MODE_MASK 0x0001 /* LDO6_LP_MODE */
+#define WM831X_LDO6_LP_MODE_SHIFT 0 /* LDO6_LP_MODE */
+#define WM831X_LDO6_LP_MODE_WIDTH 1 /* LDO6_LP_MODE */
+
+/*
+ * R16504 (0x4078) - LDO6 ON Control
+ */
+#define WM831X_LDO6_ON_SLOT_MASK 0xE000 /* LDO6_ON_SLOT - [15:13] */
+#define WM831X_LDO6_ON_SLOT_SHIFT 13 /* LDO6_ON_SLOT - [15:13] */
+#define WM831X_LDO6_ON_SLOT_WIDTH 3 /* LDO6_ON_SLOT - [15:13] */
+#define WM831X_LDO6_ON_MODE 0x0100 /* LDO6_ON_MODE */
+#define WM831X_LDO6_ON_MODE_MASK 0x0100 /* LDO6_ON_MODE */
+#define WM831X_LDO6_ON_MODE_SHIFT 8 /* LDO6_ON_MODE */
+#define WM831X_LDO6_ON_MODE_WIDTH 1 /* LDO6_ON_MODE */
+#define WM831X_LDO6_ON_VSEL_MASK 0x001F /* LDO6_ON_VSEL - [4:0] */
+#define WM831X_LDO6_ON_VSEL_SHIFT 0 /* LDO6_ON_VSEL - [4:0] */
+#define WM831X_LDO6_ON_VSEL_WIDTH 5 /* LDO6_ON_VSEL - [4:0] */
+
+/*
+ * R16505 (0x4079) - LDO6 SLEEP Control
+ */
+#define WM831X_LDO6_SLP_SLOT_MASK 0xE000 /* LDO6_SLP_SLOT - [15:13] */
+#define WM831X_LDO6_SLP_SLOT_SHIFT 13 /* LDO6_SLP_SLOT - [15:13] */
+#define WM831X_LDO6_SLP_SLOT_WIDTH 3 /* LDO6_SLP_SLOT - [15:13] */
+#define WM831X_LDO6_SLP_MODE 0x0100 /* LDO6_SLP_MODE */
+#define WM831X_LDO6_SLP_MODE_MASK 0x0100 /* LDO6_SLP_MODE */
+#define WM831X_LDO6_SLP_MODE_SHIFT 8 /* LDO6_SLP_MODE */
+#define WM831X_LDO6_SLP_MODE_WIDTH 1 /* LDO6_SLP_MODE */
+#define WM831X_LDO6_SLP_VSEL_MASK 0x001F /* LDO6_SLP_VSEL - [4:0] */
+#define WM831X_LDO6_SLP_VSEL_SHIFT 0 /* LDO6_SLP_VSEL - [4:0] */
+#define WM831X_LDO6_SLP_VSEL_WIDTH 5 /* LDO6_SLP_VSEL - [4:0] */
+
+/*
+ * R16506 (0x407A) - LDO7 Control
+ */
+#define WM831X_LDO7_ERR_ACT_MASK 0xC000 /* LDO7_ERR_ACT - [15:14] */
+#define WM831X_LDO7_ERR_ACT_SHIFT 14 /* LDO7_ERR_ACT - [15:14] */
+#define WM831X_LDO7_ERR_ACT_WIDTH 2 /* LDO7_ERR_ACT - [15:14] */
+#define WM831X_LDO7_HWC_SRC_MASK 0x1800 /* LDO7_HWC_SRC - [12:11] */
+#define WM831X_LDO7_HWC_SRC_SHIFT 11 /* LDO7_HWC_SRC - [12:11] */
+#define WM831X_LDO7_HWC_SRC_WIDTH 2 /* LDO7_HWC_SRC - [12:11] */
+#define WM831X_LDO7_HWC_VSEL 0x0400 /* LDO7_HWC_VSEL */
+#define WM831X_LDO7_HWC_VSEL_MASK 0x0400 /* LDO7_HWC_VSEL */
+#define WM831X_LDO7_HWC_VSEL_SHIFT 10 /* LDO7_HWC_VSEL */
+#define WM831X_LDO7_HWC_VSEL_WIDTH 1 /* LDO7_HWC_VSEL */
+#define WM831X_LDO7_HWC_MODE_MASK 0x0300 /* LDO7_HWC_MODE - [9:8] */
+#define WM831X_LDO7_HWC_MODE_SHIFT 8 /* LDO7_HWC_MODE - [9:8] */
+#define WM831X_LDO7_HWC_MODE_WIDTH 2 /* LDO7_HWC_MODE - [9:8] */
+#define WM831X_LDO7_FLT 0x0080 /* LDO7_FLT */
+#define WM831X_LDO7_FLT_MASK 0x0080 /* LDO7_FLT */
+#define WM831X_LDO7_FLT_SHIFT 7 /* LDO7_FLT */
+#define WM831X_LDO7_FLT_WIDTH 1 /* LDO7_FLT */
+#define WM831X_LDO7_SWI 0x0040 /* LDO7_SWI */
+#define WM831X_LDO7_SWI_MASK 0x0040 /* LDO7_SWI */
+#define WM831X_LDO7_SWI_SHIFT 6 /* LDO7_SWI */
+#define WM831X_LDO7_SWI_WIDTH 1 /* LDO7_SWI */
+
+/*
+ * R16507 (0x407B) - LDO7 ON Control
+ */
+#define WM831X_LDO7_ON_SLOT_MASK 0xE000 /* LDO7_ON_SLOT - [15:13] */
+#define WM831X_LDO7_ON_SLOT_SHIFT 13 /* LDO7_ON_SLOT - [15:13] */
+#define WM831X_LDO7_ON_SLOT_WIDTH 3 /* LDO7_ON_SLOT - [15:13] */
+#define WM831X_LDO7_ON_MODE 0x0100 /* LDO7_ON_MODE */
+#define WM831X_LDO7_ON_MODE_MASK 0x0100 /* LDO7_ON_MODE */
+#define WM831X_LDO7_ON_MODE_SHIFT 8 /* LDO7_ON_MODE */
+#define WM831X_LDO7_ON_MODE_WIDTH 1 /* LDO7_ON_MODE */
+#define WM831X_LDO7_ON_VSEL_MASK 0x001F /* LDO7_ON_VSEL - [4:0] */
+#define WM831X_LDO7_ON_VSEL_SHIFT 0 /* LDO7_ON_VSEL - [4:0] */
+#define WM831X_LDO7_ON_VSEL_WIDTH 5 /* LDO7_ON_VSEL - [4:0] */
+
+/*
+ * R16508 (0x407C) - LDO7 SLEEP Control
+ */
+#define WM831X_LDO7_SLP_SLOT_MASK 0xE000 /* LDO7_SLP_SLOT - [15:13] */
+#define WM831X_LDO7_SLP_SLOT_SHIFT 13 /* LDO7_SLP_SLOT - [15:13] */
+#define WM831X_LDO7_SLP_SLOT_WIDTH 3 /* LDO7_SLP_SLOT - [15:13] */
+#define WM831X_LDO7_SLP_MODE 0x0100 /* LDO7_SLP_MODE */
+#define WM831X_LDO7_SLP_MODE_MASK 0x0100 /* LDO7_SLP_MODE */
+#define WM831X_LDO7_SLP_MODE_SHIFT 8 /* LDO7_SLP_MODE */
+#define WM831X_LDO7_SLP_MODE_WIDTH 1 /* LDO7_SLP_MODE */
+#define WM831X_LDO7_SLP_VSEL_MASK 0x001F /* LDO7_SLP_VSEL - [4:0] */
+#define WM831X_LDO7_SLP_VSEL_SHIFT 0 /* LDO7_SLP_VSEL - [4:0] */
+#define WM831X_LDO7_SLP_VSEL_WIDTH 5 /* LDO7_SLP_VSEL - [4:0] */
+
+/*
+ * R16509 (0x407D) - LDO8 Control
+ */
+#define WM831X_LDO8_ERR_ACT_MASK 0xC000 /* LDO8_ERR_ACT - [15:14] */
+#define WM831X_LDO8_ERR_ACT_SHIFT 14 /* LDO8_ERR_ACT - [15:14] */
+#define WM831X_LDO8_ERR_ACT_WIDTH 2 /* LDO8_ERR_ACT - [15:14] */
+#define WM831X_LDO8_HWC_SRC_MASK 0x1800 /* LDO8_HWC_SRC - [12:11] */
+#define WM831X_LDO8_HWC_SRC_SHIFT 11 /* LDO8_HWC_SRC - [12:11] */
+#define WM831X_LDO8_HWC_SRC_WIDTH 2 /* LDO8_HWC_SRC - [12:11] */
+#define WM831X_LDO8_HWC_VSEL 0x0400 /* LDO8_HWC_VSEL */
+#define WM831X_LDO8_HWC_VSEL_MASK 0x0400 /* LDO8_HWC_VSEL */
+#define WM831X_LDO8_HWC_VSEL_SHIFT 10 /* LDO8_HWC_VSEL */
+#define WM831X_LDO8_HWC_VSEL_WIDTH 1 /* LDO8_HWC_VSEL */
+#define WM831X_LDO8_HWC_MODE_MASK 0x0300 /* LDO8_HWC_MODE - [9:8] */
+#define WM831X_LDO8_HWC_MODE_SHIFT 8 /* LDO8_HWC_MODE - [9:8] */
+#define WM831X_LDO8_HWC_MODE_WIDTH 2 /* LDO8_HWC_MODE - [9:8] */
+#define WM831X_LDO8_FLT 0x0080 /* LDO8_FLT */
+#define WM831X_LDO8_FLT_MASK 0x0080 /* LDO8_FLT */
+#define WM831X_LDO8_FLT_SHIFT 7 /* LDO8_FLT */
+#define WM831X_LDO8_FLT_WIDTH 1 /* LDO8_FLT */
+#define WM831X_LDO8_SWI 0x0040 /* LDO8_SWI */
+#define WM831X_LDO8_SWI_MASK 0x0040 /* LDO8_SWI */
+#define WM831X_LDO8_SWI_SHIFT 6 /* LDO8_SWI */
+#define WM831X_LDO8_SWI_WIDTH 1 /* LDO8_SWI */
+
+/*
+ * R16510 (0x407E) - LDO8 ON Control
+ */
+#define WM831X_LDO8_ON_SLOT_MASK 0xE000 /* LDO8_ON_SLOT - [15:13] */
+#define WM831X_LDO8_ON_SLOT_SHIFT 13 /* LDO8_ON_SLOT - [15:13] */
+#define WM831X_LDO8_ON_SLOT_WIDTH 3 /* LDO8_ON_SLOT - [15:13] */
+#define WM831X_LDO8_ON_MODE 0x0100 /* LDO8_ON_MODE */
+#define WM831X_LDO8_ON_MODE_MASK 0x0100 /* LDO8_ON_MODE */
+#define WM831X_LDO8_ON_MODE_SHIFT 8 /* LDO8_ON_MODE */
+#define WM831X_LDO8_ON_MODE_WIDTH 1 /* LDO8_ON_MODE */
+#define WM831X_LDO8_ON_VSEL_MASK 0x001F /* LDO8_ON_VSEL - [4:0] */
+#define WM831X_LDO8_ON_VSEL_SHIFT 0 /* LDO8_ON_VSEL - [4:0] */
+#define WM831X_LDO8_ON_VSEL_WIDTH 5 /* LDO8_ON_VSEL - [4:0] */
+
+/*
+ * R16511 (0x407F) - LDO8 SLEEP Control
+ */
+#define WM831X_LDO8_SLP_SLOT_MASK 0xE000 /* LDO8_SLP_SLOT - [15:13] */
+#define WM831X_LDO8_SLP_SLOT_SHIFT 13 /* LDO8_SLP_SLOT - [15:13] */
+#define WM831X_LDO8_SLP_SLOT_WIDTH 3 /* LDO8_SLP_SLOT - [15:13] */
+#define WM831X_LDO8_SLP_MODE 0x0100 /* LDO8_SLP_MODE */
+#define WM831X_LDO8_SLP_MODE_MASK 0x0100 /* LDO8_SLP_MODE */
+#define WM831X_LDO8_SLP_MODE_SHIFT 8 /* LDO8_SLP_MODE */
+#define WM831X_LDO8_SLP_MODE_WIDTH 1 /* LDO8_SLP_MODE */
+#define WM831X_LDO8_SLP_VSEL_MASK 0x001F /* LDO8_SLP_VSEL - [4:0] */
+#define WM831X_LDO8_SLP_VSEL_SHIFT 0 /* LDO8_SLP_VSEL - [4:0] */
+#define WM831X_LDO8_SLP_VSEL_WIDTH 5 /* LDO8_SLP_VSEL - [4:0] */
+
+/*
+ * R16512 (0x4080) - LDO9 Control
+ */
+#define WM831X_LDO9_ERR_ACT_MASK 0xC000 /* LDO9_ERR_ACT - [15:14] */
+#define WM831X_LDO9_ERR_ACT_SHIFT 14 /* LDO9_ERR_ACT - [15:14] */
+#define WM831X_LDO9_ERR_ACT_WIDTH 2 /* LDO9_ERR_ACT - [15:14] */
+#define WM831X_LDO9_HWC_SRC_MASK 0x1800 /* LDO9_HWC_SRC - [12:11] */
+#define WM831X_LDO9_HWC_SRC_SHIFT 11 /* LDO9_HWC_SRC - [12:11] */
+#define WM831X_LDO9_HWC_SRC_WIDTH 2 /* LDO9_HWC_SRC - [12:11] */
+#define WM831X_LDO9_HWC_VSEL 0x0400 /* LDO9_HWC_VSEL */
+#define WM831X_LDO9_HWC_VSEL_MASK 0x0400 /* LDO9_HWC_VSEL */
+#define WM831X_LDO9_HWC_VSEL_SHIFT 10 /* LDO9_HWC_VSEL */
+#define WM831X_LDO9_HWC_VSEL_WIDTH 1 /* LDO9_HWC_VSEL */
+#define WM831X_LDO9_HWC_MODE_MASK 0x0300 /* LDO9_HWC_MODE - [9:8] */
+#define WM831X_LDO9_HWC_MODE_SHIFT 8 /* LDO9_HWC_MODE - [9:8] */
+#define WM831X_LDO9_HWC_MODE_WIDTH 2 /* LDO9_HWC_MODE - [9:8] */
+#define WM831X_LDO9_FLT 0x0080 /* LDO9_FLT */
+#define WM831X_LDO9_FLT_MASK 0x0080 /* LDO9_FLT */
+#define WM831X_LDO9_FLT_SHIFT 7 /* LDO9_FLT */
+#define WM831X_LDO9_FLT_WIDTH 1 /* LDO9_FLT */
+#define WM831X_LDO9_SWI 0x0040 /* LDO9_SWI */
+#define WM831X_LDO9_SWI_MASK 0x0040 /* LDO9_SWI */
+#define WM831X_LDO9_SWI_SHIFT 6 /* LDO9_SWI */
+#define WM831X_LDO9_SWI_WIDTH 1 /* LDO9_SWI */
+
+/*
+ * R16513 (0x4081) - LDO9 ON Control
+ */
+#define WM831X_LDO9_ON_SLOT_MASK 0xE000 /* LDO9_ON_SLOT - [15:13] */
+#define WM831X_LDO9_ON_SLOT_SHIFT 13 /* LDO9_ON_SLOT - [15:13] */
+#define WM831X_LDO9_ON_SLOT_WIDTH 3 /* LDO9_ON_SLOT - [15:13] */
+#define WM831X_LDO9_ON_MODE 0x0100 /* LDO9_ON_MODE */
+#define WM831X_LDO9_ON_MODE_MASK 0x0100 /* LDO9_ON_MODE */
+#define WM831X_LDO9_ON_MODE_SHIFT 8 /* LDO9_ON_MODE */
+#define WM831X_LDO9_ON_MODE_WIDTH 1 /* LDO9_ON_MODE */
+#define WM831X_LDO9_ON_VSEL_MASK 0x001F /* LDO9_ON_VSEL - [4:0] */
+#define WM831X_LDO9_ON_VSEL_SHIFT 0 /* LDO9_ON_VSEL - [4:0] */
+#define WM831X_LDO9_ON_VSEL_WIDTH 5 /* LDO9_ON_VSEL - [4:0] */
+
+/*
+ * R16514 (0x4082) - LDO9 SLEEP Control
+ */
+#define WM831X_LDO9_SLP_SLOT_MASK 0xE000 /* LDO9_SLP_SLOT - [15:13] */
+#define WM831X_LDO9_SLP_SLOT_SHIFT 13 /* LDO9_SLP_SLOT - [15:13] */
+#define WM831X_LDO9_SLP_SLOT_WIDTH 3 /* LDO9_SLP_SLOT - [15:13] */
+#define WM831X_LDO9_SLP_MODE 0x0100 /* LDO9_SLP_MODE */
+#define WM831X_LDO9_SLP_MODE_MASK 0x0100 /* LDO9_SLP_MODE */
+#define WM831X_LDO9_SLP_MODE_SHIFT 8 /* LDO9_SLP_MODE */
+#define WM831X_LDO9_SLP_MODE_WIDTH 1 /* LDO9_SLP_MODE */
+#define WM831X_LDO9_SLP_VSEL_MASK 0x001F /* LDO9_SLP_VSEL - [4:0] */
+#define WM831X_LDO9_SLP_VSEL_SHIFT 0 /* LDO9_SLP_VSEL - [4:0] */
+#define WM831X_LDO9_SLP_VSEL_WIDTH 5 /* LDO9_SLP_VSEL - [4:0] */
+
+/*
+ * R16515 (0x4083) - LDO10 Control
+ */
+#define WM831X_LDO10_ERR_ACT_MASK 0xC000 /* LDO10_ERR_ACT - [15:14] */
+#define WM831X_LDO10_ERR_ACT_SHIFT 14 /* LDO10_ERR_ACT - [15:14] */
+#define WM831X_LDO10_ERR_ACT_WIDTH 2 /* LDO10_ERR_ACT - [15:14] */
+#define WM831X_LDO10_HWC_SRC_MASK 0x1800 /* LDO10_HWC_SRC - [12:11] */
+#define WM831X_LDO10_HWC_SRC_SHIFT 11 /* LDO10_HWC_SRC - [12:11] */
+#define WM831X_LDO10_HWC_SRC_WIDTH 2 /* LDO10_HWC_SRC - [12:11] */
+#define WM831X_LDO10_HWC_VSEL 0x0400 /* LDO10_HWC_VSEL */
+#define WM831X_LDO10_HWC_VSEL_MASK 0x0400 /* LDO10_HWC_VSEL */
+#define WM831X_LDO10_HWC_VSEL_SHIFT 10 /* LDO10_HWC_VSEL */
+#define WM831X_LDO10_HWC_VSEL_WIDTH 1 /* LDO10_HWC_VSEL */
+#define WM831X_LDO10_HWC_MODE_MASK 0x0300 /* LDO10_HWC_MODE - [9:8] */
+#define WM831X_LDO10_HWC_MODE_SHIFT 8 /* LDO10_HWC_MODE - [9:8] */
+#define WM831X_LDO10_HWC_MODE_WIDTH 2 /* LDO10_HWC_MODE - [9:8] */
+#define WM831X_LDO10_FLT 0x0080 /* LDO10_FLT */
+#define WM831X_LDO10_FLT_MASK 0x0080 /* LDO10_FLT */
+#define WM831X_LDO10_FLT_SHIFT 7 /* LDO10_FLT */
+#define WM831X_LDO10_FLT_WIDTH 1 /* LDO10_FLT */
+#define WM831X_LDO10_SWI 0x0040 /* LDO10_SWI */
+#define WM831X_LDO10_SWI_MASK 0x0040 /* LDO10_SWI */
+#define WM831X_LDO10_SWI_SHIFT 6 /* LDO10_SWI */
+#define WM831X_LDO10_SWI_WIDTH 1 /* LDO10_SWI */
+
+/*
+ * R16516 (0x4084) - LDO10 ON Control
+ */
+#define WM831X_LDO10_ON_SLOT_MASK 0xE000 /* LDO10_ON_SLOT - [15:13] */
+#define WM831X_LDO10_ON_SLOT_SHIFT 13 /* LDO10_ON_SLOT - [15:13] */
+#define WM831X_LDO10_ON_SLOT_WIDTH 3 /* LDO10_ON_SLOT - [15:13] */
+#define WM831X_LDO10_ON_MODE 0x0100 /* LDO10_ON_MODE */
+#define WM831X_LDO10_ON_MODE_MASK 0x0100 /* LDO10_ON_MODE */
+#define WM831X_LDO10_ON_MODE_SHIFT 8 /* LDO10_ON_MODE */
+#define WM831X_LDO10_ON_MODE_WIDTH 1 /* LDO10_ON_MODE */
+#define WM831X_LDO10_ON_VSEL_MASK 0x001F /* LDO10_ON_VSEL - [4:0] */
+#define WM831X_LDO10_ON_VSEL_SHIFT 0 /* LDO10_ON_VSEL - [4:0] */
+#define WM831X_LDO10_ON_VSEL_WIDTH 5 /* LDO10_ON_VSEL - [4:0] */
+
+/*
+ * R16517 (0x4085) - LDO10 SLEEP Control
+ */
+#define WM831X_LDO10_SLP_SLOT_MASK 0xE000 /* LDO10_SLP_SLOT - [15:13] */
+#define WM831X_LDO10_SLP_SLOT_SHIFT 13 /* LDO10_SLP_SLOT - [15:13] */
+#define WM831X_LDO10_SLP_SLOT_WIDTH 3 /* LDO10_SLP_SLOT - [15:13] */
+#define WM831X_LDO10_SLP_MODE 0x0100 /* LDO10_SLP_MODE */
+#define WM831X_LDO10_SLP_MODE_MASK 0x0100 /* LDO10_SLP_MODE */
+#define WM831X_LDO10_SLP_MODE_SHIFT 8 /* LDO10_SLP_MODE */
+#define WM831X_LDO10_SLP_MODE_WIDTH 1 /* LDO10_SLP_MODE */
+#define WM831X_LDO10_SLP_VSEL_MASK 0x001F /* LDO10_SLP_VSEL - [4:0] */
+#define WM831X_LDO10_SLP_VSEL_SHIFT 0 /* LDO10_SLP_VSEL - [4:0] */
+#define WM831X_LDO10_SLP_VSEL_WIDTH 5 /* LDO10_SLP_VSEL - [4:0] */
+
+/*
+ * R16519 (0x4087) - LDO11 ON Control
+ */
+#define WM831X_LDO11_ON_SLOT_MASK 0xE000 /* LDO11_ON_SLOT - [15:13] */
+#define WM831X_LDO11_ON_SLOT_SHIFT 13 /* LDO11_ON_SLOT - [15:13] */
+#define WM831X_LDO11_ON_SLOT_WIDTH 3 /* LDO11_ON_SLOT - [15:13] */
+#define WM831X_LDO11_OFFENA 0x1000 /* LDO11_OFFENA */
+#define WM831X_LDO11_OFFENA_MASK 0x1000 /* LDO11_OFFENA */
+#define WM831X_LDO11_OFFENA_SHIFT 12 /* LDO11_OFFENA */
+#define WM831X_LDO11_OFFENA_WIDTH 1 /* LDO11_OFFENA */
+#define WM831X_LDO11_VSEL_SRC 0x0080 /* LDO11_VSEL_SRC */
+#define WM831X_LDO11_VSEL_SRC_MASK 0x0080 /* LDO11_VSEL_SRC */
+#define WM831X_LDO11_VSEL_SRC_SHIFT 7 /* LDO11_VSEL_SRC */
+#define WM831X_LDO11_VSEL_SRC_WIDTH 1 /* LDO11_VSEL_SRC */
+#define WM831X_LDO11_ON_VSEL_MASK 0x000F /* LDO11_ON_VSEL - [3:0] */
+#define WM831X_LDO11_ON_VSEL_SHIFT 0 /* LDO11_ON_VSEL - [3:0] */
+#define WM831X_LDO11_ON_VSEL_WIDTH 4 /* LDO11_ON_VSEL - [3:0] */
+
+/*
+ * R16520 (0x4088) - LDO11 SLEEP Control
+ */
+#define WM831X_LDO11_SLP_SLOT_MASK 0xE000 /* LDO11_SLP_SLOT - [15:13] */
+#define WM831X_LDO11_SLP_SLOT_SHIFT 13 /* LDO11_SLP_SLOT - [15:13] */
+#define WM831X_LDO11_SLP_SLOT_WIDTH 3 /* LDO11_SLP_SLOT - [15:13] */
+#define WM831X_LDO11_SLP_VSEL_MASK 0x000F /* LDO11_SLP_VSEL - [3:0] */
+#define WM831X_LDO11_SLP_VSEL_SHIFT 0 /* LDO11_SLP_VSEL - [3:0] */
+#define WM831X_LDO11_SLP_VSEL_WIDTH 4 /* LDO11_SLP_VSEL - [3:0] */
+
+/*
+ * R16526 (0x408E) - Power Good Source 1
+ */
+#define WM831X_DC4_OK 0x0008 /* DC4_OK */
+#define WM831X_DC4_OK_MASK 0x0008 /* DC4_OK */
+#define WM831X_DC4_OK_SHIFT 3 /* DC4_OK */
+#define WM831X_DC4_OK_WIDTH 1 /* DC4_OK */
+#define WM831X_DC3_OK 0x0004 /* DC3_OK */
+#define WM831X_DC3_OK_MASK 0x0004 /* DC3_OK */
+#define WM831X_DC3_OK_SHIFT 2 /* DC3_OK */
+#define WM831X_DC3_OK_WIDTH 1 /* DC3_OK */
+#define WM831X_DC2_OK 0x0002 /* DC2_OK */
+#define WM831X_DC2_OK_MASK 0x0002 /* DC2_OK */
+#define WM831X_DC2_OK_SHIFT 1 /* DC2_OK */
+#define WM831X_DC2_OK_WIDTH 1 /* DC2_OK */
+#define WM831X_DC1_OK 0x0001 /* DC1_OK */
+#define WM831X_DC1_OK_MASK 0x0001 /* DC1_OK */
+#define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */
+#define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */
+
+/*
+ * R16527 (0x408F) - Power Good Source 2
+ */
+#define WM831X_LDO10_OK 0x0200 /* LDO10_OK */
+#define WM831X_LDO10_OK_MASK 0x0200 /* LDO10_OK */
+#define WM831X_LDO10_OK_SHIFT 9 /* LDO10_OK */
+#define WM831X_LDO10_OK_WIDTH 1 /* LDO10_OK */
+#define WM831X_LDO9_OK 0x0100 /* LDO9_OK */
+#define WM831X_LDO9_OK_MASK 0x0100 /* LDO9_OK */
+#define WM831X_LDO9_OK_SHIFT 8 /* LDO9_OK */
+#define WM831X_LDO9_OK_WIDTH 1 /* LDO9_OK */
+#define WM831X_LDO8_OK 0x0080 /* LDO8_OK */
+#define WM831X_LDO8_OK_MASK 0x0080 /* LDO8_OK */
+#define WM831X_LDO8_OK_SHIFT 7 /* LDO8_OK */
+#define WM831X_LDO8_OK_WIDTH 1 /* LDO8_OK */
+#define WM831X_LDO7_OK 0x0040 /* LDO7_OK */
+#define WM831X_LDO7_OK_MASK 0x0040 /* LDO7_OK */
+#define WM831X_LDO7_OK_SHIFT 6 /* LDO7_OK */
+#define WM831X_LDO7_OK_WIDTH 1 /* LDO7_OK */
+#define WM831X_LDO6_OK 0x0020 /* LDO6_OK */
+#define WM831X_LDO6_OK_MASK 0x0020 /* LDO6_OK */
+#define WM831X_LDO6_OK_SHIFT 5 /* LDO6_OK */
+#define WM831X_LDO6_OK_WIDTH 1 /* LDO6_OK */
+#define WM831X_LDO5_OK 0x0010 /* LDO5_OK */
+#define WM831X_LDO5_OK_MASK 0x0010 /* LDO5_OK */
+#define WM831X_LDO5_OK_SHIFT 4 /* LDO5_OK */
+#define WM831X_LDO5_OK_WIDTH 1 /* LDO5_OK */
+#define WM831X_LDO4_OK 0x0008 /* LDO4_OK */
+#define WM831X_LDO4_OK_MASK 0x0008 /* LDO4_OK */
+#define WM831X_LDO4_OK_SHIFT 3 /* LDO4_OK */
+#define WM831X_LDO4_OK_WIDTH 1 /* LDO4_OK */
+#define WM831X_LDO3_OK 0x0004 /* LDO3_OK */
+#define WM831X_LDO3_OK_MASK 0x0004 /* LDO3_OK */
+#define WM831X_LDO3_OK_SHIFT 2 /* LDO3_OK */
+#define WM831X_LDO3_OK_WIDTH 1 /* LDO3_OK */
+#define WM831X_LDO2_OK 0x0002 /* LDO2_OK */
+#define WM831X_LDO2_OK_MASK 0x0002 /* LDO2_OK */
+#define WM831X_LDO2_OK_SHIFT 1 /* LDO2_OK */
+#define WM831X_LDO2_OK_WIDTH 1 /* LDO2_OK */
+#define WM831X_LDO1_OK 0x0001 /* LDO1_OK */
+#define WM831X_LDO1_OK_MASK 0x0001 /* LDO1_OK */
+#define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */
+#define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */
+
+#define WM831X_ISINK_MAX_ISEL 56
+extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL];
+
+#endif
diff --git a/include/linux/mfd/wm831x/watchdog.h b/include/linux/mfd/wm831x/watchdog.h
new file mode 100644
index 00000000000..97a99b52956
--- /dev/null
+++ b/include/linux/mfd/wm831x/watchdog.h
@@ -0,0 +1,52 @@
+/*
+ * include/linux/mfd/wm831x/watchdog.h -- Watchdog for WM831x
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM831X_WATCHDOG_H__
+#define __MFD_WM831X_WATCHDOG_H__
+
+
+/*
+ * R16388 (0x4004) - Watchdog
+ */
+#define WM831X_WDOG_ENA 0x8000 /* WDOG_ENA */
+#define WM831X_WDOG_ENA_MASK 0x8000 /* WDOG_ENA */
+#define WM831X_WDOG_ENA_SHIFT 15 /* WDOG_ENA */
+#define WM831X_WDOG_ENA_WIDTH 1 /* WDOG_ENA */
+#define WM831X_WDOG_DEBUG 0x4000 /* WDOG_DEBUG */
+#define WM831X_WDOG_DEBUG_MASK 0x4000 /* WDOG_DEBUG */
+#define WM831X_WDOG_DEBUG_SHIFT 14 /* WDOG_DEBUG */
+#define WM831X_WDOG_DEBUG_WIDTH 1 /* WDOG_DEBUG */
+#define WM831X_WDOG_RST_SRC 0x2000 /* WDOG_RST_SRC */
+#define WM831X_WDOG_RST_SRC_MASK 0x2000 /* WDOG_RST_SRC */
+#define WM831X_WDOG_RST_SRC_SHIFT 13 /* WDOG_RST_SRC */
+#define WM831X_WDOG_RST_SRC_WIDTH 1 /* WDOG_RST_SRC */
+#define WM831X_WDOG_SLPENA 0x1000 /* WDOG_SLPENA */
+#define WM831X_WDOG_SLPENA_MASK 0x1000 /* WDOG_SLPENA */
+#define WM831X_WDOG_SLPENA_SHIFT 12 /* WDOG_SLPENA */
+#define WM831X_WDOG_SLPENA_WIDTH 1 /* WDOG_SLPENA */
+#define WM831X_WDOG_RESET 0x0800 /* WDOG_RESET */
+#define WM831X_WDOG_RESET_MASK 0x0800 /* WDOG_RESET */
+#define WM831X_WDOG_RESET_SHIFT 11 /* WDOG_RESET */
+#define WM831X_WDOG_RESET_WIDTH 1 /* WDOG_RESET */
+#define WM831X_WDOG_SECACT_MASK 0x0300 /* WDOG_SECACT - [9:8] */
+#define WM831X_WDOG_SECACT_SHIFT 8 /* WDOG_SECACT - [9:8] */
+#define WM831X_WDOG_SECACT_WIDTH 2 /* WDOG_SECACT - [9:8] */
+#define WM831X_WDOG_PRIMACT_MASK 0x0030 /* WDOG_PRIMACT - [5:4] */
+#define WM831X_WDOG_PRIMACT_SHIFT 4 /* WDOG_PRIMACT - [5:4] */
+#define WM831X_WDOG_PRIMACT_WIDTH 2 /* WDOG_PRIMACT - [5:4] */
+#define WM831X_WDOG_TO_MASK 0x0007 /* WDOG_TO - [2:0] */
+#define WM831X_WDOG_TO_SHIFT 0 /* WDOG_TO - [2:0] */
+#define WM831X_WDOG_TO_WIDTH 3 /* WDOG_TO - [2:0] */
+
+#endif
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 42cca672f34..1d595de6a05 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -605,6 +605,11 @@ struct wm8350_irq {
void *data;
};
+struct wm8350_hwmon {
+ struct platform_device *pdev;
+ struct device *classdev;
+};
+
struct wm8350 {
struct device *dev;
@@ -621,7 +626,6 @@ struct wm8350 {
struct mutex auxadc_mutex;
/* Interrupt handling */
- struct work_struct irq_work;
struct mutex irq_mutex; /* IRQ table mutex */
struct wm8350_irq irq[WM8350_NUM_IRQ];
int chip_irq;
@@ -629,6 +633,7 @@ struct wm8350 {
/* Client devices */
struct wm8350_codec codec;
struct wm8350_gpio gpio;
+ struct wm8350_hwmon hwmon;
struct wm8350_pmic pmic;
struct wm8350_power power;
struct wm8350_rtc rtc;
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 225f733e753..ce1be708ca1 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -193,6 +193,8 @@ void *rdev_get_drvdata(struct regulator_dev *rdev);
struct device *rdev_get_dev(struct regulator_dev *rdev);
int rdev_get_id(struct regulator_dev *rdev);
+int regulator_mode_to_status(unsigned int);
+
void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
#endif
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index eb1423a0078..68e212ff9dd 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -85,7 +85,6 @@ struct intc_desc symbol __initdata = { \
}
#endif
-unsigned int intc_evt2irq(unsigned int vector);
void __init register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
diff --git a/include/linux/taskstats_kern.h b/include/linux/taskstats_kern.h
index 7e9680f4afd..3398f455326 100644
--- a/include/linux/taskstats_kern.h
+++ b/include/linux/taskstats_kern.h
@@ -9,7 +9,6 @@
#include <linux/taskstats.h>
#include <linux/sched.h>
-#include <net/genetlink.h>
#ifdef CONFIG_TASKSTATS
extern struct kmem_cache *taskstats_cache;
diff --git a/include/linux/time.h b/include/linux/time.h
index ea16c1a01d5..56787c09334 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -75,7 +75,7 @@ extern unsigned long mktime(const unsigned int year, const unsigned int mon,
const unsigned int day, const unsigned int hour,
const unsigned int min, const unsigned int sec);
-extern void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec);
+extern void set_normalized_timespec(struct timespec *ts, time_t sec, s64 nsec);
extern struct timespec timespec_add_safe(const struct timespec lhs,
const struct timespec rhs);
@@ -101,7 +101,8 @@ extern struct timespec xtime;
extern struct timespec wall_to_monotonic;
extern seqlock_t xtime_lock;
-extern unsigned long read_persistent_clock(void);
+extern void read_persistent_clock(struct timespec *ts);
+extern void read_boot_clock(struct timespec *ts);
extern int update_persistent_clock(struct timespec now);
extern int no_sync_cmos_clock __read_mostly;
void timekeeping_init(void);
@@ -109,6 +110,8 @@ extern int timekeeping_suspended;
unsigned long get_seconds(void);
struct timespec current_kernel_time(void);
+struct timespec __current_kernel_time(void); /* does not hold xtime_lock */
+struct timespec get_monotonic_coarse(void);
#define CURRENT_TIME (current_kernel_time())
#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 })
@@ -147,6 +150,7 @@ extern struct timespec timespec_trunc(struct timespec t, unsigned gran);
extern int timekeeping_valid_for_hres(void);
extern void update_wall_time(void);
extern void update_xtime_cache(u64 nsec);
+extern void timekeeping_leap_insert(int leapsecond);
struct tms;
extern void do_sys_times(struct tms *);
@@ -241,6 +245,8 @@ struct itimerval {
#define CLOCK_PROCESS_CPUTIME_ID 2
#define CLOCK_THREAD_CPUTIME_ID 3
#define CLOCK_MONOTONIC_RAW 4
+#define CLOCK_REALTIME_COARSE 5
+#define CLOCK_MONOTONIC_COARSE 6
/*
* The IDs of various hardware clocks:
diff --git a/include/linux/timer.h b/include/linux/timer.h
index be62ec2ebea..a2d1eb6cb3f 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -175,11 +175,6 @@ extern int mod_timer_pinned(struct timer_list *timer, unsigned long expires);
/*
* Return when the next timer-wheel timeout occurs (in absolute jiffies),
- * locks the timer base:
- */
-extern unsigned long next_timer_interrupt(void);
-/*
- * Return when the next timer-wheel timeout occurs (in absolute jiffies),
* locks the timer base and does the comparison against the given
* jiffie.
*/
diff --git a/include/linux/usb/m66592.h b/include/linux/usb/m66592.h
new file mode 100644
index 00000000000..cda9625e7df
--- /dev/null
+++ b/include/linux/usb/m66592.h
@@ -0,0 +1,44 @@
+/*
+ * M66592 driver platform data
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#ifndef __LINUX_USB_M66592_H
+#define __LINUX_USB_M66592_H
+
+#define M66592_PLATDATA_XTAL_12MHZ 0x01
+#define M66592_PLATDATA_XTAL_24MHZ 0x02
+#define M66592_PLATDATA_XTAL_48MHZ 0x03
+
+struct m66592_platdata {
+ /* one = on chip controller, zero = external controller */
+ unsigned on_chip:1;
+
+ /* one = big endian, zero = little endian */
+ unsigned endian:1;
+
+ /* (external controller only) M66592_PLATDATA_XTAL_nnMHZ */
+ unsigned xtal:2;
+
+ /* (external controller only) one = 3.3V, zero = 1.5V */
+ unsigned vif:1;
+
+};
+
+#endif /* __LINUX_USB_M66592_H */
+
diff --git a/include/linux/usb/r8a66597.h b/include/linux/usb/r8a66597.h
index e9f0384fa20..26d21673405 100644
--- a/include/linux/usb/r8a66597.h
+++ b/include/linux/usb/r8a66597.h
@@ -28,9 +28,12 @@
#define R8A66597_PLATDATA_XTAL_48MHZ 0x03
struct r8a66597_platdata {
- /* This ops can controll port power instead of DVSTCTR register. */
+ /* This callback can control port power instead of DVSTCTR register. */
void (*port_power)(int port, int power);
+ /* set one = on chip controller, set zero = external controller */
+ unsigned on_chip:1;
+
/* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
unsigned xtal:2;
@@ -40,5 +43,373 @@ struct r8a66597_platdata {
/* set one = big endian, set zero = little endian */
unsigned endian:1;
};
-#endif
+
+/* Register definitions */
+#define SYSCFG0 0x00
+#define SYSCFG1 0x02
+#define SYSSTS0 0x04
+#define SYSSTS1 0x06
+#define DVSTCTR0 0x08
+#define DVSTCTR1 0x0A
+#define TESTMODE 0x0C
+#define PINCFG 0x0E
+#define DMA0CFG 0x10
+#define DMA1CFG 0x12
+#define CFIFO 0x14
+#define D0FIFO 0x18
+#define D1FIFO 0x1C
+#define CFIFOSEL 0x20
+#define CFIFOCTR 0x22
+#define CFIFOSIE 0x24
+#define D0FIFOSEL 0x28
+#define D0FIFOCTR 0x2A
+#define D1FIFOSEL 0x2C
+#define D1FIFOCTR 0x2E
+#define INTENB0 0x30
+#define INTENB1 0x32
+#define INTENB2 0x34
+#define BRDYENB 0x36
+#define NRDYENB 0x38
+#define BEMPENB 0x3A
+#define SOFCFG 0x3C
+#define INTSTS0 0x40
+#define INTSTS1 0x42
+#define INTSTS2 0x44
+#define BRDYSTS 0x46
+#define NRDYSTS 0x48
+#define BEMPSTS 0x4A
+#define FRMNUM 0x4C
+#define UFRMNUM 0x4E
+#define USBADDR 0x50
+#define USBREQ 0x54
+#define USBVAL 0x56
+#define USBINDX 0x58
+#define USBLENG 0x5A
+#define DCPCFG 0x5C
+#define DCPMAXP 0x5E
+#define DCPCTR 0x60
+#define PIPESEL 0x64
+#define PIPECFG 0x68
+#define PIPEBUF 0x6A
+#define PIPEMAXP 0x6C
+#define PIPEPERI 0x6E
+#define PIPE1CTR 0x70
+#define PIPE2CTR 0x72
+#define PIPE3CTR 0x74
+#define PIPE4CTR 0x76
+#define PIPE5CTR 0x78
+#define PIPE6CTR 0x7A
+#define PIPE7CTR 0x7C
+#define PIPE8CTR 0x7E
+#define PIPE9CTR 0x80
+#define PIPE1TRE 0x90
+#define PIPE1TRN 0x92
+#define PIPE2TRE 0x94
+#define PIPE2TRN 0x96
+#define PIPE3TRE 0x98
+#define PIPE3TRN 0x9A
+#define PIPE4TRE 0x9C
+#define PIPE4TRN 0x9E
+#define PIPE5TRE 0xA0
+#define PIPE5TRN 0xA2
+#define DEVADD0 0xD0
+#define DEVADD1 0xD2
+#define DEVADD2 0xD4
+#define DEVADD3 0xD6
+#define DEVADD4 0xD8
+#define DEVADD5 0xDA
+#define DEVADD6 0xDC
+#define DEVADD7 0xDE
+#define DEVADD8 0xE0
+#define DEVADD9 0xE2
+#define DEVADDA 0xE4
+
+/* System Configuration Control Register */
+#define XTAL 0xC000 /* b15-14: Crystal selection */
+#define XTAL48 0x8000 /* 48MHz */
+#define XTAL24 0x4000 /* 24MHz */
+#define XTAL12 0x0000 /* 12MHz */
+#define XCKE 0x2000 /* b13: External clock enable */
+#define PLLC 0x0800 /* b11: PLL control */
+#define SCKE 0x0400 /* b10: USB clock enable */
+#define PCSDIS 0x0200 /* b9: not CS wakeup */
+#define LPSME 0x0100 /* b8: Low power sleep mode */
+#define HSE 0x0080 /* b7: Hi-speed enable */
+#define DCFM 0x0040 /* b6: Controller function select */
+#define DRPD 0x0020 /* b5: D+/- pull down control */
+#define DPRPU 0x0010 /* b4: D+ pull up control */
+#define USBE 0x0001 /* b0: USB module operation enable */
+
+/* System Configuration Status Register */
+#define OVCBIT 0x8000 /* b15-14: Over-current bit */
+#define OVCMON 0xC000 /* b15-14: Over-current monitor */
+#define SOFEA 0x0020 /* b5: SOF monitor */
+#define IDMON 0x0004 /* b3: ID-pin monitor */
+#define LNST 0x0003 /* b1-0: D+, D- line status */
+#define SE1 0x0003 /* SE1 */
+#define FS_KSTS 0x0002 /* Full-Speed K State */
+#define FS_JSTS 0x0001 /* Full-Speed J State */
+#define LS_JSTS 0x0002 /* Low-Speed J State */
+#define LS_KSTS 0x0001 /* Low-Speed K State */
+#define SE0 0x0000 /* SE0 */
+
+/* Device State Control Register */
+#define EXTLP0 0x0400 /* b10: External port */
+#define VBOUT 0x0200 /* b9: VBUS output */
+#define WKUP 0x0100 /* b8: Remote wakeup */
+#define RWUPE 0x0080 /* b7: Remote wakeup sense */
+#define USBRST 0x0040 /* b6: USB reset enable */
+#define RESUME 0x0020 /* b5: Resume enable */
+#define UACT 0x0010 /* b4: USB bus enable */
+#define RHST 0x0007 /* b1-0: Reset handshake status */
+#define HSPROC 0x0004 /* HS handshake is processing */
+#define HSMODE 0x0003 /* Hi-Speed mode */
+#define FSMODE 0x0002 /* Full-Speed mode */
+#define LSMODE 0x0001 /* Low-Speed mode */
+#define UNDECID 0x0000 /* Undecided */
+
+/* Test Mode Register */
+#define UTST 0x000F /* b3-0: Test select */
+#define H_TST_PACKET 0x000C /* HOST TEST Packet */
+#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
+#define H_TST_K 0x000A /* HOST TEST K */
+#define H_TST_J 0x0009 /* HOST TEST J */
+#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
+#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
+#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
+#define P_TST_K 0x0002 /* PERI TEST K */
+#define P_TST_J 0x0001 /* PERI TEST J */
+#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
+
+/* Data Pin Configuration Register */
+#define LDRV 0x8000 /* b15: Drive Current Adjust */
+#define VIF1 0x0000 /* VIF = 1.8V */
+#define VIF3 0x8000 /* VIF = 3.3V */
+#define INTA 0x0001 /* b1: USB INT-pin active */
+
+/* DMAx Pin Configuration Register */
+#define DREQA 0x4000 /* b14: Dreq active select */
+#define BURST 0x2000 /* b13: Burst mode */
+#define DACKA 0x0400 /* b10: Dack active select */
+#define DFORM 0x0380 /* b9-7: DMA mode select */
+#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
+#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
+#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
+#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
+#define DENDA 0x0040 /* b6: Dend active select */
+#define PKTM 0x0020 /* b5: Packet mode */
+#define DENDE 0x0010 /* b4: Dend enable */
+#define OBUS 0x0004 /* b2: OUTbus mode */
+
+/* CFIFO/DxFIFO Port Select Register */
+#define RCNT 0x8000 /* b15: Read count mode */
+#define REW 0x4000 /* b14: Buffer rewind */
+#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
+#define DREQE 0x1000 /* b12: DREQ output enable */
+#define MBW_8 0x0000 /* 8bit */
+#define MBW_16 0x0400 /* 16bit */
+#define MBW_32 0x0800 /* 32bit */
+#define BIGEND 0x0100 /* b8: Big endian mode */
+#define BYTE_LITTLE 0x0000 /* little dendian */
+#define BYTE_BIG 0x0100 /* big endifan */
+#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
+#define CURPIPE 0x000F /* b2-0: PIPE select */
+
+/* CFIFO/DxFIFO Port Control Register */
+#define BVAL 0x8000 /* b15: Buffer valid flag */
+#define BCLR 0x4000 /* b14: Buffer clear */
+#define FRDY 0x2000 /* b13: FIFO ready */
+#define DTLN 0x0FFF /* b11-0: FIFO received data length */
+
+/* Interrupt Enable Register 0 */
+#define VBSE 0x8000 /* b15: VBUS interrupt */
+#define RSME 0x4000 /* b14: Resume interrupt */
+#define SOFE 0x2000 /* b13: Frame update interrupt */
+#define DVSE 0x1000 /* b12: Device state transition interrupt */
+#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
+#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
+#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
+#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
+
+/* Interrupt Enable Register 1 */
+#define OVRCRE 0x8000 /* b15: Over-current interrupt */
+#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
+#define DTCHE 0x1000 /* b12: Detach sense interrupt */
+#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
+#define EOFERRE 0x0040 /* b6: EOF error interrupt */
+#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
+#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
+
+/* BRDY Interrupt Enable/Status Register */
+#define BRDY9 0x0200 /* b9: PIPE9 */
+#define BRDY8 0x0100 /* b8: PIPE8 */
+#define BRDY7 0x0080 /* b7: PIPE7 */
+#define BRDY6 0x0040 /* b6: PIPE6 */
+#define BRDY5 0x0020 /* b5: PIPE5 */
+#define BRDY4 0x0010 /* b4: PIPE4 */
+#define BRDY3 0x0008 /* b3: PIPE3 */
+#define BRDY2 0x0004 /* b2: PIPE2 */
+#define BRDY1 0x0002 /* b1: PIPE1 */
+#define BRDY0 0x0001 /* b1: PIPE0 */
+
+/* NRDY Interrupt Enable/Status Register */
+#define NRDY9 0x0200 /* b9: PIPE9 */
+#define NRDY8 0x0100 /* b8: PIPE8 */
+#define NRDY7 0x0080 /* b7: PIPE7 */
+#define NRDY6 0x0040 /* b6: PIPE6 */
+#define NRDY5 0x0020 /* b5: PIPE5 */
+#define NRDY4 0x0010 /* b4: PIPE4 */
+#define NRDY3 0x0008 /* b3: PIPE3 */
+#define NRDY2 0x0004 /* b2: PIPE2 */
+#define NRDY1 0x0002 /* b1: PIPE1 */
+#define NRDY0 0x0001 /* b1: PIPE0 */
+
+/* BEMP Interrupt Enable/Status Register */
+#define BEMP9 0x0200 /* b9: PIPE9 */
+#define BEMP8 0x0100 /* b8: PIPE8 */
+#define BEMP7 0x0080 /* b7: PIPE7 */
+#define BEMP6 0x0040 /* b6: PIPE6 */
+#define BEMP5 0x0020 /* b5: PIPE5 */
+#define BEMP4 0x0010 /* b4: PIPE4 */
+#define BEMP3 0x0008 /* b3: PIPE3 */
+#define BEMP2 0x0004 /* b2: PIPE2 */
+#define BEMP1 0x0002 /* b1: PIPE1 */
+#define BEMP0 0x0001 /* b0: PIPE0 */
+
+/* SOF Pin Configuration Register */
+#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
+#define BRDYM 0x0040 /* b6: BRDY clear timing */
+#define INTL 0x0020 /* b5: Interrupt sense select */
+#define EDGESTS 0x0010 /* b4: */
+#define SOFMODE 0x000C /* b3-2: SOF pin select */
+#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
+#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
+#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
+
+/* Interrupt Status Register 0 */
+#define VBINT 0x8000 /* b15: VBUS interrupt */
+#define RESM 0x4000 /* b14: Resume interrupt */
+#define SOFR 0x2000 /* b13: SOF frame update interrupt */
+#define DVST 0x1000 /* b12: Device state transition interrupt */
+#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
+#define BEMP 0x0400 /* b10: Buffer empty interrupt */
+#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
+#define BRDY 0x0100 /* b8: Buffer ready interrupt */
+#define VBSTS 0x0080 /* b7: VBUS input port */
+#define DVSQ 0x0070 /* b6-4: Device state */
+#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
+#define DS_SPD_ADDR 0x0060 /* Suspend Address */
+#define DS_SPD_DFLT 0x0050 /* Suspend Default */
+#define DS_SPD_POWR 0x0040 /* Suspend Powered */
+#define DS_SUSP 0x0040 /* Suspend */
+#define DS_CNFG 0x0030 /* Configured */
+#define DS_ADDS 0x0020 /* Address */
+#define DS_DFLT 0x0010 /* Default */
+#define DS_POWR 0x0000 /* Powered */
+#define DVSQS 0x0030 /* b5-4: Device state */
+#define VALID 0x0008 /* b3: Setup packet detected flag */
+#define CTSQ 0x0007 /* b2-0: Control transfer stage */
+#define CS_SQER 0x0006 /* Sequence error */
+#define CS_WRND 0x0005 /* Control write nodata status stage */
+#define CS_WRSS 0x0004 /* Control write status stage */
+#define CS_WRDS 0x0003 /* Control write data stage */
+#define CS_RDSS 0x0002 /* Control read status stage */
+#define CS_RDDS 0x0001 /* Control read data stage */
+#define CS_IDST 0x0000 /* Idle or setup stage */
+
+/* Interrupt Status Register 1 */
+#define OVRCR 0x8000 /* b15: Over-current interrupt */
+#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
+#define DTCH 0x1000 /* b12: Detach sense interrupt */
+#define ATTCH 0x0800 /* b11: Attach sense interrupt */
+#define EOFERR 0x0040 /* b6: EOF-error interrupt */
+#define SIGN 0x0020 /* b5: Setup ignore interrupt */
+#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
+
+/* Frame Number Register */
+#define OVRN 0x8000 /* b15: Overrun error */
+#define CRCE 0x4000 /* b14: Received data error */
+#define FRNM 0x07FF /* b10-0: Frame number */
+
+/* Micro Frame Number Register */
+#define UFRNM 0x0007 /* b2-0: Micro frame number */
+
+/* Default Control Pipe Maxpacket Size Register */
+/* Pipe Maxpacket Size Register */
+#define DEVSEL 0xF000 /* b15-14: Device address select */
+#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
+
+/* Default Control Pipe Control Register */
+#define BSTS 0x8000 /* b15: Buffer status */
+#define SUREQ 0x4000 /* b14: Send USB request */
+#define CSCLR 0x2000 /* b13: complete-split status clear */
+#define CSSTS 0x1000 /* b12: complete-split status */
+#define SUREQCLR 0x0800 /* b11: stop setup request */
+#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
+#define SQSET 0x0080 /* b7: Sequence toggle bit set */
+#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
+#define PBUSY 0x0020 /* b5: pipe busy */
+#define PINGE 0x0010 /* b4: ping enable */
+#define CCPL 0x0004 /* b2: Enable control transfer complete */
+#define PID 0x0003 /* b1-0: Response PID */
+#define PID_STALL11 0x0003 /* STALL */
+#define PID_STALL 0x0002 /* STALL */
+#define PID_BUF 0x0001 /* BUF */
+#define PID_NAK 0x0000 /* NAK */
+
+/* Pipe Window Select Register */
+#define PIPENM 0x0007 /* b2-0: Pipe select */
+
+/* Pipe Configuration Register */
+#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
+#define R8A66597_ISO 0xC000 /* Isochronous */
+#define R8A66597_INT 0x8000 /* Interrupt */
+#define R8A66597_BULK 0x4000 /* Bulk */
+#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
+#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
+#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
+#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
+#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
+#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
+
+/* Pipe Buffer Configuration Register */
+#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
+#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
+#define PIPE0BUF 256
+#define PIPExBUF 64
+
+/* Pipe Maxpacket Size Register */
+#define MXPS 0x07FF /* b10-0: Maxpacket size */
+
+/* Pipe Cycle Configuration Register */
+#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
+#define IITV 0x0007 /* b2-0: Isochronous interval */
+
+/* Pipex Control Register */
+#define BSTS 0x8000 /* b15: Buffer status */
+#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
+#define CSCLR 0x2000 /* b13: complete-split status clear */
+#define CSSTS 0x1000 /* b12: complete-split status */
+#define ATREPM 0x0400 /* b10: Auto repeat mode */
+#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
+#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
+#define SQSET 0x0080 /* b7: Sequence toggle bit set */
+#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
+#define PBUSY 0x0020 /* b5: pipe busy */
+#define PID 0x0003 /* b1-0: Response PID */
+
+/* PIPExTRE */
+#define TRENB 0x0200 /* b9: Transaction counter enable */
+#define TRCLR 0x0100 /* b8: Transaction counter clear */
+
+/* PIPExTRN */
+#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
+
+/* DEVADDx */
+#define UPPHUB 0x7800
+#define HUBPORT 0x0700
+#define USBSPD 0x00C0
+#define RTPORT 0x0001
+
+#endif /* __LINUX_USB_R8A66597_H */
diff --git a/include/trace/events/ext4.h b/include/trace/events/ext4.h
index 8d433c4e370..c1bd8f1e8b9 100644
--- a/include/trace/events/ext4.h
+++ b/include/trace/events/ext4.h
@@ -5,10 +5,15 @@
#define _TRACE_EXT4_H
#include <linux/writeback.h>
-#include "../../../fs/ext4/ext4.h"
-#include "../../../fs/ext4/mballoc.h"
#include <linux/tracepoint.h>
+struct ext4_allocation_context;
+struct ext4_allocation_request;
+struct ext4_prealloc_space;
+struct ext4_inode_info;
+
+#define EXT4_I(inode) (container_of(inode, struct ext4_inode_info, vfs_inode))
+
TRACE_EVENT(ext4_free_inode,
TP_PROTO(struct inode *inode),
@@ -33,8 +38,8 @@ TRACE_EVENT(ext4_free_inode,
),
TP_printk("dev %s ino %lu mode %d uid %u gid %u blocks %llu",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->mode,
- __entry->uid, __entry->gid,
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->mode, __entry->uid, __entry->gid,
(unsigned long long) __entry->blocks)
);
@@ -56,7 +61,8 @@ TRACE_EVENT(ext4_request_inode,
),
TP_printk("dev %s dir %lu mode %d",
- jbd2_dev_to_name(__entry->dev), __entry->dir, __entry->mode)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->dir,
+ __entry->mode)
);
TRACE_EVENT(ext4_allocate_inode,
@@ -79,7 +85,8 @@ TRACE_EVENT(ext4_allocate_inode,
),
TP_printk("dev %s ino %lu dir %lu mode %d",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->dir, __entry->mode)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ (unsigned long) __entry->dir, __entry->mode)
);
TRACE_EVENT(ext4_write_begin,
@@ -106,8 +113,8 @@ TRACE_EVENT(ext4_write_begin,
),
TP_printk("dev %s ino %lu pos %llu len %u flags %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pos, __entry->len,
- __entry->flags)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pos, __entry->len, __entry->flags)
);
TRACE_EVENT(ext4_ordered_write_end,
@@ -133,8 +140,8 @@ TRACE_EVENT(ext4_ordered_write_end,
),
TP_printk("dev %s ino %lu pos %llu len %u copied %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pos, __entry->len,
- __entry->copied)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pos, __entry->len, __entry->copied)
);
TRACE_EVENT(ext4_writeback_write_end,
@@ -160,8 +167,8 @@ TRACE_EVENT(ext4_writeback_write_end,
),
TP_printk("dev %s ino %lu pos %llu len %u copied %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pos, __entry->len,
- __entry->copied)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pos, __entry->len, __entry->copied)
);
TRACE_EVENT(ext4_journalled_write_end,
@@ -186,8 +193,8 @@ TRACE_EVENT(ext4_journalled_write_end,
),
TP_printk("dev %s ino %lu pos %llu len %u copied %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pos, __entry->len,
- __entry->copied)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pos, __entry->len, __entry->copied)
);
TRACE_EVENT(ext4_writepage,
@@ -209,7 +216,8 @@ TRACE_EVENT(ext4_writepage,
),
TP_printk("dev %s ino %lu page_index %lu",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->index)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->index)
);
TRACE_EVENT(ext4_da_writepages,
@@ -243,14 +251,49 @@ TRACE_EVENT(ext4_da_writepages,
__entry->range_cyclic = wbc->range_cyclic;
),
- TP_printk("dev %s ino %lu nr_t_write %ld pages_skipped %ld range_start %llu range_end %llu nonblocking %d for_kupdate %d for_reclaim %d range_cyclic %d",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->nr_to_write,
+ TP_printk("dev %s ino %lu nr_to_write %ld pages_skipped %ld range_start %llu range_end %llu nonblocking %d for_kupdate %d for_reclaim %d range_cyclic %d",
+ jbd2_dev_to_name(__entry->dev),
+ (unsigned long) __entry->ino, __entry->nr_to_write,
__entry->pages_skipped, __entry->range_start,
__entry->range_end, __entry->nonblocking,
__entry->for_kupdate, __entry->for_reclaim,
__entry->range_cyclic)
);
+TRACE_EVENT(ext4_da_write_pages,
+ TP_PROTO(struct inode *inode, struct mpage_da_data *mpd),
+
+ TP_ARGS(inode, mpd),
+
+ TP_STRUCT__entry(
+ __field( dev_t, dev )
+ __field( ino_t, ino )
+ __field( __u64, b_blocknr )
+ __field( __u32, b_size )
+ __field( __u32, b_state )
+ __field( unsigned long, first_page )
+ __field( int, io_done )
+ __field( int, pages_written )
+ ),
+
+ TP_fast_assign(
+ __entry->dev = inode->i_sb->s_dev;
+ __entry->ino = inode->i_ino;
+ __entry->b_blocknr = mpd->b_blocknr;
+ __entry->b_size = mpd->b_size;
+ __entry->b_state = mpd->b_state;
+ __entry->first_page = mpd->first_page;
+ __entry->io_done = mpd->io_done;
+ __entry->pages_written = mpd->pages_written;
+ ),
+
+ TP_printk("dev %s ino %lu b_blocknr %llu b_size %u b_state 0x%04x first_page %lu io_done %d pages_written %d",
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->b_blocknr, __entry->b_size,
+ __entry->b_state, __entry->first_page,
+ __entry->io_done, __entry->pages_written)
+);
+
TRACE_EVENT(ext4_da_writepages_result,
TP_PROTO(struct inode *inode, struct writeback_control *wbc,
int ret, int pages_written),
@@ -280,7 +323,8 @@ TRACE_EVENT(ext4_da_writepages_result,
),
TP_printk("dev %s ino %lu ret %d pages_written %d pages_skipped %ld congestion %d more_io %d no_nrwrite_index_update %d",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->ret,
+ jbd2_dev_to_name(__entry->dev),
+ (unsigned long) __entry->ino, __entry->ret,
__entry->pages_written, __entry->pages_skipped,
__entry->encountered_congestion, __entry->more_io,
__entry->no_nrwrite_index_update)
@@ -309,8 +353,8 @@ TRACE_EVENT(ext4_da_write_begin,
),
TP_printk("dev %s ino %lu pos %llu len %u flags %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pos, __entry->len,
- __entry->flags)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pos, __entry->len, __entry->flags)
);
TRACE_EVENT(ext4_da_write_end,
@@ -336,8 +380,8 @@ TRACE_EVENT(ext4_da_write_end,
),
TP_printk("dev %s ino %lu pos %llu len %u copied %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pos, __entry->len,
- __entry->copied)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pos, __entry->len, __entry->copied)
);
TRACE_EVENT(ext4_discard_blocks,
@@ -387,8 +431,8 @@ TRACE_EVENT(ext4_mb_new_inode_pa,
),
TP_printk("dev %s ino %lu pstart %llu len %u lstart %llu",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pa_pstart,
- __entry->pa_len, __entry->pa_lstart)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pa_pstart, __entry->pa_len, __entry->pa_lstart)
);
TRACE_EVENT(ext4_mb_new_group_pa,
@@ -415,8 +459,8 @@ TRACE_EVENT(ext4_mb_new_group_pa,
),
TP_printk("dev %s ino %lu pstart %llu len %u lstart %llu",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->pa_pstart,
- __entry->pa_len, __entry->pa_lstart)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->pa_pstart, __entry->pa_len, __entry->pa_lstart)
);
TRACE_EVENT(ext4_mb_release_inode_pa,
@@ -442,8 +486,8 @@ TRACE_EVENT(ext4_mb_release_inode_pa,
),
TP_printk("dev %s ino %lu block %llu count %u",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->block,
- __entry->count)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->block, __entry->count)
);
TRACE_EVENT(ext4_mb_release_group_pa,
@@ -488,7 +532,7 @@ TRACE_EVENT(ext4_discard_preallocations,
),
TP_printk("dev %s ino %lu",
- jbd2_dev_to_name(__entry->dev), __entry->ino)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino)
);
TRACE_EVENT(ext4_mb_discard_preallocations,
@@ -543,8 +587,8 @@ TRACE_EVENT(ext4_request_blocks,
),
TP_printk("dev %s ino %lu flags %u len %u lblk %llu goal %llu lleft %llu lright %llu pleft %llu pright %llu ",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->flags,
- __entry->len,
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->flags, __entry->len,
(unsigned long long) __entry->logical,
(unsigned long long) __entry->goal,
(unsigned long long) __entry->lleft,
@@ -587,8 +631,8 @@ TRACE_EVENT(ext4_allocate_blocks,
),
TP_printk("dev %s ino %lu flags %u len %u block %llu lblk %llu goal %llu lleft %llu lright %llu pleft %llu pright %llu ",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->flags,
- __entry->len, __entry->block,
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->flags, __entry->len, __entry->block,
(unsigned long long) __entry->logical,
(unsigned long long) __entry->goal,
(unsigned long long) __entry->lleft,
@@ -621,8 +665,8 @@ TRACE_EVENT(ext4_free_blocks,
),
TP_printk("dev %s ino %lu block %llu count %lu metadata %d",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->block,
- __entry->count, __entry->metadata)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->block, __entry->count, __entry->metadata)
);
TRACE_EVENT(ext4_sync_file,
@@ -645,8 +689,8 @@ TRACE_EVENT(ext4_sync_file,
),
TP_printk("dev %s ino %ld parent %ld datasync %d ",
- jbd2_dev_to_name(__entry->dev), __entry->ino, __entry->parent,
- __entry->datasync)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ (unsigned long) __entry->parent, __entry->datasync)
);
TRACE_EVENT(ext4_sync_fs,
@@ -669,6 +713,30 @@ TRACE_EVENT(ext4_sync_fs,
__entry->wait)
);
+TRACE_EVENT(ext4_alloc_da_blocks,
+ TP_PROTO(struct inode *inode),
+
+ TP_ARGS(inode),
+
+ TP_STRUCT__entry(
+ __field( dev_t, dev )
+ __field( ino_t, ino )
+ __field( unsigned int, data_blocks )
+ __field( unsigned int, meta_blocks )
+ ),
+
+ TP_fast_assign(
+ __entry->dev = inode->i_sb->s_dev;
+ __entry->ino = inode->i_ino;
+ __entry->data_blocks = EXT4_I(inode)->i_reserved_data_blocks;
+ __entry->meta_blocks = EXT4_I(inode)->i_reserved_meta_blocks;
+ ),
+
+ TP_printk("dev %s ino %lu data_blocks %u meta_blocks %u",
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino,
+ __entry->data_blocks, __entry->meta_blocks)
+);
+
#endif /* _TRACE_EXT4_H */
/* This part must be outside protection */
diff --git a/include/trace/events/jbd2.h b/include/trace/events/jbd2.h
index 10813fa0c8d..b851f0b4701 100644
--- a/include/trace/events/jbd2.h
+++ b/include/trace/events/jbd2.h
@@ -159,7 +159,7 @@ TRACE_EVENT(jbd2_submit_inode_data,
),
TP_printk("dev %s ino %lu",
- jbd2_dev_to_name(__entry->dev), __entry->ino)
+ jbd2_dev_to_name(__entry->dev), (unsigned long) __entry->ino)
);
#endif /* _TRACE_JBD2_H */