introduce-fiq-hdq.patch

This adds a platform driver and device which performs HDQ
battery protocol using a single GPIO pin which is set
through platform data.

HDQ has some hard latency requirements which can't
be met if interrupts are enabled, so normally using
a GPIO for this will require blocking out all other
interrupts and processes for several milliseconds
per register being read or written.

This HDQ protocol engine is a FSM implemented inside the
the FIQ ISR and regulated by timer interrupts happening
at 20us intervals.  The path through the FSM on any
"clock" is very short and should be over with in ~
1us.  Because FIQ has guaranteed latencies of <1us,
it means we can service the HDQ protocol without
blocking interrupts or any other process other than
the caller that is waiting for the result. It's pretty
cool performance from 1 GPIO ;-)

Due to it being hard to do locking from the FIQ ISR
the code simply sleeps 10ms or whatever the scheduler
gives it and checks if the transfer took place yet.

This platform driver doesn't have any knowledge about
the device it is talking to, it just knows it is a
HDQ device.  It exports three functions for read, write
and confirming HDQ is initialized.  It also exports two
/sys nodes that are usable by humans, one dumps the whole
127 register HDQ register space

# cat /sys/devices/platform/gta02-hdq.0/hdq/dump
00 44 55 00 00 00 ba 04 a2 0d 50 00 00 00 00 00
00 00 9a 1a 00 00 ff ff ff ff 29 00 00 00 80 2b
00 00 00 00 00 00 ff ff 00 00 00 00 00 32 af 06
a0 d8 37 4e 00 00 00 00 00 00 00 34 2e 03 b4 e7
00 00 06 00 41 00 4c 02 00 00 00 00 00 00 00 00
83 02 00 00 94 09 59 b9 a5 0d 7f 21 00 00 7a ff
df ff 62 ff a7 04 2e 05 00 00 00 01 00 07 00 00
2a 78 36 67 7b b5 1b a9 af 19 38 89 63 57 42 7c
#

and the other allows to set one register

# echo 2 170 > /sys/devices/platform/gta02-hdq.0/hdq/write

writes 0xAA into register 2.

Signed-off-by: Andy Green <andy@openmoko.com>

0 files changed, 0 insertions, 0 deletions