diff options
| author | merge <null@invalid> | 2009-02-24 01:49:53 +0000 |
|---|---|---|
| committer | Andy Green <agreen@octopus.localdomain> | 2009-02-24 01:49:53 +0000 |
| commit | 7fafbf75a0978b79e32c6a0ce15a776fea6d8481 (patch) | |
| tree | 0d4eacd74a04b0bd9c0e2c926aefe07b8f48a38d /sound/soc/s3c24xx/s3c-i2s-v2.c | |
| parent | 1c6a91fef7cb2e0fc4f41ddcfff74565b2a7659e (diff) | |
MERGE-via-pending-tracking-hist-MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-s3c64xx-dma-support-1235439162-1235439227
pending-tracking-hist top was MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-s3c64xx-dma-support-1235439162-1235439227 / 3d6a1b21cf5fbdb6250d781b0a4900a7a0768aa1 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-stable-tracking-hist-MERGE-via-mokopatches-tracking-s3c64xx-dma-support-1235439162
stable-tracking-hist top was MERGE-via-mokopatches-tracking-s3c64xx-dma-support-1235439162 / 893e864e65adffc9eb085ed4f8b552a31dcec840 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-mokopatches-tracking-hist-s3c64xx-dma-support
mokopatches-tracking-hist top was s3c64xx-dma-support / 2515f9a1d53d19b1e61d639875aedcbe7929666e ... parent commitmessage:
From: Ben Dooks <ben@simtec.co.uk>
S3C64XX: DMA support
Add support for the DMA blocks in the S3C64XX series
of CPUS, which are based on the ARM PL080 PrimeCell
system.
Unfortunately, these DMA controllers diverge from the
PL080 design by adding another DMA controller register
and configuration for OneNAND.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Diffstat (limited to 'sound/soc/s3c24xx/s3c-i2s-v2.c')
| -rw-r--r-- | sound/soc/s3c24xx/s3c-i2s-v2.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/sound/soc/s3c24xx/s3c-i2s-v2.c b/sound/soc/s3c24xx/s3c-i2s-v2.c index 1dda7c85622..8a57f77d9a2 100644 --- a/sound/soc/s3c24xx/s3c-i2s-v2.c +++ b/sound/soc/s3c24xx/s3c-i2s-v2.c @@ -257,6 +257,25 @@ static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai, iismod = readl(i2s->regs + S3C2412_IISMOD); DBG("hw_params r: IISMOD: %x \n", iismod); +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) +#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK +#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE +#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL +#endif + +#if defined(CONFIG_CPU_S3C64XX) +/* From Rev1.1 datasheet, we have two master and two slave modes: + * IMS[11:10]: + * 00 = master mode, fed from PCLK + * 01 = master mode, fed from CLKAUDIO + * 10 = slave mode, using PCLK + * 11 = slave mode, using I2SCLK + */ +#define IISMOD_MASTER_MASK (1 << 11) +#define IISMOD_SLAVE (1 << 11) +#define IISMOD_MASTER (0x0) +#endif + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: i2s->master = 0; |