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-rw-r--r--arch/arm/kernel/armksyms.c3
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c27
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c3
-rw-r--r--arch/arm/mm/proc-v6.S2
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h176
6 files changed, 198 insertions, 17 deletions
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index b713c44c6fb..835d450797a 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -41,7 +41,10 @@ extern void fp_enter(void);
* This has a special calling convention; it doesn't
* modify any of the usual registers, except for LR.
*/
+#define EXPORT_CRC_ALIAS(sym) __CRC_SYMBOL(sym, "")
+
#define EXPORT_SYMBOL_ALIAS(sym,orig) \
+ EXPORT_CRC_ALIAS(sym) \
const struct kernel_symbol __ksymtab_##sym \
__attribute__((section("__ksymtab"))) = \
{ (unsigned long)&orig, #sym };
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index aa92e370883..2b544363c07 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -453,8 +453,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
res[0].name = "PCI I/O Space";
- res[0].start = 0x00001000;
- res[0].end = 0xffff0000;
+ res[0].start = 0x00000000;
+ res[0].end = 0x0000ffff;
res[0].flags = IORESOURCE_IO;
res[1].name = "PCI Memory Space";
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index c6335f51907..4ff4393ef0e 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -56,21 +56,24 @@ static struct resource coyote_uart_resource = {
.flags = IORESOURCE_MEM,
};
-static struct plat_serial8250_port coyote_uart_data = {
- .mapbase = IXP4XX_UART2_BASE_PHYS,
- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
- .irq = IRQ_IXP4XX_UART2,
- .flags = UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = IXP4XX_UART_XTAL,
+static struct plat_serial8250_port coyote_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
};
static struct platform_device coyote_uart = {
.name = "serial8250",
.id = 0,
.dev = {
- .platform_data = &coyote_uart_data,
+ .platform_data = coyote_uart_data,
},
.num_resources = 1,
.resource = &coyote_uart_resource,
@@ -87,10 +90,10 @@ static void __init coyote_init(void)
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
if (machine_is_ixdpg425()) {
- coyote_uart_data.membase =
+ coyote_uart_data[0].membase =
(char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
- coyote_uart_data.mapbase = IXP4XX_UART1_BASE_PHYS;
- coyote_uart_data.irq = IRQ_IXP4XX_UART1;
+ coyote_uart_data[0].mapbase = IXP4XX_UART1_BASE_PHYS;
+ coyote_uart_data[0].irq = IRQ_IXP4XX_UART1;
}
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index f2e9c0ea050..c2ba759e994 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -95,7 +95,8 @@ static struct plat_serial8250_port ixdp425_uart_data[] = {
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
- }
+ },
+ { },
};
static struct platform_device ixdp425_uart = {
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index e3d8510f434..352db98ee26 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -200,7 +200,7 @@ __v6_setup:
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
#ifdef CONFIG_VFP
mrc p15, 0, r0, c1, c0, 2
- orr r0, r0, #(3 << 20)
+ orr r0, r0, #(0xf << 20)
mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
#endif
mrc p15, 0, r0, c1, c0, 0 @ read control register
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index c27b9d3079a..7495026e2c1 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -3,7 +3,7 @@
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
- * Copyright (C) 2002-2004 MontaVista Software, Inc.
+ * Copyright (C) 2002-2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -383,6 +383,180 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
*vaddr++ = inl(io_addr);
}
+#define __is_io_address(p) (((unsigned long)p >= 0x0) && \
+ ((unsigned long)p <= 0x0000ffff))
+static inline unsigned int
+__ixp4xx_ioread8(void __iomem *port)
+{
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inb((unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return (unsigned int)__raw_readb((u32)port);
+#else
+ return (unsigned int)__ixp4xx_readb((u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_insb(port, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsb((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_readsb(port, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread16(void __iomem *port)
+{
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inw((unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return le16_to_cpu(__raw_readw((u32)port));
+#else
+ return (unsigned int)__ixp4xx_readw((u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_insw(port, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsw((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_readsw(port, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread32(void __iomem *port)
+{
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inl((unsigned int)port);
+ else {
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return le32_to_cpu(__raw_readl((u32)port));
+#else
+ return (unsigned int)__ixp4xx_readl((u32)port);
+#endif
+ }
+}
+
+static inline void
+__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_insl(port, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsl((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_readsl(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8(u8 value, void __iomem *port)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outb(value, (unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writeb(value, (u32)port);
+#else
+ __ixp4xx_writeb(value, (u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outsb(port, vaddr, count);
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writesb((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_writesb(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16(u16 value, void __iomem *port)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outw(value, (unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writew(cpu_to_le16(value), (u32)port);
+#else
+ __ixp4xx_writew(value, (u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outsw(port, vaddr, count);
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsw((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_writesw(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32(u32 value, void __iomem *port)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outl(value, (unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writel(cpu_to_le32(value), (u32)port);
+#else
+ __ixp4xx_writel(value, (u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outsl(port, vaddr, count);
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsl((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_outsl(port, vaddr, count);
+#endif
+}
+
+#define ioread8(p) __ixp4xx_ioread8(p)
+#define ioread16(p) __ixp4xx_ioread16(p)
+#define ioread32(p) __ixp4xx_ioread32(p)
+
+#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
+#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
+#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
+
+#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
+#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
+#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
+
+#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
+#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
+#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
+
+#define ioport_map(port, nr) ((void __iomem*)port)
+#define ioport_unmap(addr)
#endif // __ASM_ARM_ARCH_IO_H
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 02:32:00 +0000