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-rw-r--r--arch/arm/mach-s3c2440/fiq_c_isr.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-gta02.c4
-rw-r--r--drivers/power/gta02_hdq.c18
3 files changed, 18 insertions, 8 deletions
diff --git a/arch/arm/mach-s3c2440/fiq_c_isr.c b/arch/arm/mach-s3c2440/fiq_c_isr.c
index 43fd6b53205..0decc35a317 100644
--- a/arch/arm/mach-s3c2440/fiq_c_isr.c
+++ b/arch/arm/mach-s3c2440/fiq_c_isr.c
@@ -230,6 +230,8 @@ static int __init sc32440_fiq_probe(struct platform_device *pdev)
ret = sysfs_create_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
if (ret)
return ret;
+
+ fiq_ready = 1;
/*
* if wanted, users can defer registration of devices
@@ -239,8 +241,6 @@ static int __init sc32440_fiq_probe(struct platform_device *pdev)
if (pdata->attach_child_devices)
(pdata->attach_child_devices)(&pdev->dev);
- fiq_ready = 1;
-
return 0;
}
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 6a77fd1cf08..9c9d5065c09 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -847,8 +847,8 @@ static void gta02_fiq_attach_child_devices(struct device *parent_device)
static struct resource sc32440_fiq_resources[] = {
[0] = {
.flags = IORESOURCE_IRQ,
- .start = IRQ_TIMER1,
- .end = IRQ_TIMER1,
+ .start = IRQ_TIMER3,
+ .end = IRQ_TIMER3,
},
};
diff --git a/drivers/power/gta02_hdq.c b/drivers/power/gta02_hdq.c
index ac52ea8be4c..d51f4c9f55a 100644
--- a/drivers/power/gta02_hdq.c
+++ b/drivers/power/gta02_hdq.c
@@ -26,6 +26,13 @@
#define HDQ_READ 0
#define HDQ_WRITE 0x80
+static int fiq_busy(void)
+{
+ int request = (volatile u8)fiq_ipc.hdq_request_ctr;
+ int transact = (volatile u8)fiq_ipc.hdq_transaction_ctr;
+
+ return (request != transact);
+}
int gta02hdq_initialized(void)
{
@@ -43,6 +50,7 @@ int gta02hdq_read(int address)
mutex_lock(&fiq_ipc.hdq_lock);
+ fiq_ipc.hdq_error = 0;
fiq_ipc.hdq_ads = address | HDQ_READ;
fiq_ipc.hdq_request_ctr++;
fiq_kick();
@@ -54,7 +62,7 @@ int gta02hdq_read(int address)
while (count_sleeps--) {
msleep(10); /* valid transaction always completes in < 10ms */
- if (fiq_ipc.hdq_request_ctr != fiq_ipc.hdq_transaction_ctr)
+ if (fiq_busy())
continue;
if (fiq_ipc.hdq_error)
@@ -63,7 +71,6 @@ int gta02hdq_read(int address)
ret = fiq_ipc.hdq_rx_data;
goto done;
}
- ret = -EINVAL;
done:
mutex_unlock(&fiq_ipc.hdq_lock);
@@ -81,6 +88,7 @@ int gta02hdq_write(int address, u8 data)
mutex_lock(&fiq_ipc.hdq_lock);
+ fiq_ipc.hdq_error = 0;
fiq_ipc.hdq_ads = address | HDQ_WRITE;
fiq_ipc.hdq_tx_data = data;
fiq_ipc.hdq_request_ctr++;
@@ -93,13 +101,15 @@ int gta02hdq_write(int address, u8 data)
while (count_sleeps--) {
msleep(10); /* valid transaction always completes in < 10ms */
- if (fiq_ipc.hdq_request_ctr != fiq_ipc.hdq_transaction_ctr)
+ if (fiq_busy())
continue; /* something bad with FIQ */
if (fiq_ipc.hdq_error)
goto done; /* didn't see a response in good time */
+
+ ret = 0;
+ goto done;
}
- ret = -EINVAL;
done:
mutex_unlock(&fiq_ipc.hdq_lock);