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-rw-r--r--drivers/video/nvidia/nv_hw.c4
-rw-r--r--drivers/video/nvidia/nv_setup.c4
-rw-r--r--drivers/video/riva/nv_driver.c2
-rw-r--r--drivers/video/riva/riva_hw.c4
4 files changed, 7 insertions, 7 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c
index d1a10549f54..ed20a9871b3 100644
--- a/drivers/video/nvidia/nv_hw.c
+++ b/drivers/video/nvidia/nv_hw.c
@@ -129,7 +129,7 @@ typedef struct {
int nvclk_khz;
char mem_page_miss;
char mem_latency;
- int memory_type;
+ u32 memory_type;
int memory_width;
char enable_video;
char gr_during_vid;
@@ -719,7 +719,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
memctrl >>= 16;
if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
- int dimm[3];
+ u32 dimm[3];
dev = pci_get_bus_and_slot(0, 2);
pci_read_config_dword(dev, 0x40, &dimm[0]);
diff --git a/drivers/video/nvidia/nv_setup.c b/drivers/video/nvidia/nv_setup.c
index 82579d3a997..d9627b57eb4 100644
--- a/drivers/video/nvidia/nv_setup.c
+++ b/drivers/video/nvidia/nv_setup.c
@@ -265,12 +265,12 @@ static void nv10GetConfig(struct nvidia_par *par)
dev = pci_get_bus_and_slot(0, 1);
if ((par->Chipset & 0xffff) == 0x01a0) {
- int amt = 0;
+ u32 amt;
pci_read_config_dword(dev, 0x7c, &amt);
par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
} else if ((par->Chipset & 0xffff) == 0x01f0) {
- int amt = 0;
+ u32 amt;
pci_read_config_dword(dev, 0x84, &amt);
par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
diff --git a/drivers/video/riva/nv_driver.c b/drivers/video/riva/nv_driver.c
index a1181149da7..f3694cf17e5 100644
--- a/drivers/video/riva/nv_driver.c
+++ b/drivers/video/riva/nv_driver.c
@@ -158,7 +158,7 @@ unsigned long riva_get_memlen(struct riva_par *par)
unsigned long memlen = 0;
unsigned int chipset = par->Chipset;
struct pci_dev* dev;
- int amt;
+ u32 amt;
switch (chip->Architecture) {
case NV_ARCH_03:
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
index 13307703a9f..78fdbf5178d 100644
--- a/drivers/video/riva/riva_hw.c
+++ b/drivers/video/riva/riva_hw.c
@@ -231,7 +231,7 @@ typedef struct {
int nvclk_khz;
char mem_page_miss;
char mem_latency;
- int memory_type;
+ u32 memory_type;
int memory_width;
char enable_video;
char gr_during_vid;
@@ -2107,7 +2107,7 @@ static void nv10GetConfig
)
{
struct pci_dev* dev;
- int amt;
+ u32 amt;
#ifdef __BIG_ENDIAN
/* turn on big endian register access */