aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-s3c6410/include/mach/spi-gpio.h36
-rw-r--r--drivers/spi/Kconfig9
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi_s3c64xx_gpio.c201
-rw-r--r--drivers/video/display/Kconfig8
-rw-r--r--drivers/video/display/Makefile1
-rw-r--r--drivers/video/display/l1k002.c278
-rw-r--r--include/linux/l1k002.h8
8 files changed, 542 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c6410/include/mach/spi-gpio.h b/arch/arm/mach-s3c6410/include/mach/spi-gpio.h
new file mode 100644
index 00000000000..35716ff0a1e
--- /dev/null
+++ b/arch/arm/mach-s3c6410/include/mach/spi-gpio.h
@@ -0,0 +1,36 @@
+/* arch/arm/mach-s3c6400/include/mach/spi-gpio.h
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - SPI Controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SPIGPIO_H
+#define __ASM_ARCH_SPIGPIO_H __FILE__
+
+struct s3c64xx_spigpio_info {
+ unsigned long pin_clk;
+ unsigned long pin_mosi;
+ unsigned long pin_miso;
+
+ int bus_num;
+ int num_chipselect;
+
+ /*
+ * FIXME: board_size and board_info DO NOT belong here.
+ * These were already removed upstream... but we still rely on them
+ * so leave for now and revisit this.
+ */
+ unsigned long board_size;
+ struct spi_board_info *board_info;
+
+ void (*chip_select)(struct s3c64xx_spigpio_info *spi, int csid, int cs);
+};
+
+
+#endif /* __ASM_ARCH_SPIGPIO_H */
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b9d0efb6803..c713addde44 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -243,6 +243,15 @@ config SPI_TLE62X0
sysfs interface, with each line presented as a kind of GPIO
exposing both switch control and diagnostic feedback.
+config SPI_S3C64XX_GPIO
+ tristate "Samsung S3C64XX series SPI by GPIO"
+ depends on ARCH_S3C64XX && EXPERIMENTAL
+ select SPI_BITBANG
+ help
+ SPI driver for Samsung S3C64XX series ARM SoCs using
+ GPIO lines to provide the SPI bus. This can be used where
+ the inbuilt hardware cannot provide the transfer mode, or
+ where the board is using non hardware connected pins.
#
# Add new SPI protocol masters in alphabetical order above this line
#
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ccf18de34e1..a55fed7f945 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
+obj-$(CONFIG_SPI_S3C64XX_GPIO) += spi_s3c64xx_gpio.o
# ... add above this line ...
# SPI protocol drivers (device/link on bus)
diff --git a/drivers/spi/spi_s3c64xx_gpio.c b/drivers/spi/spi_s3c64xx_gpio.c
new file mode 100644
index 00000000000..9ade147e80f
--- /dev/null
+++ b/drivers/spi/spi_s3c64xx_gpio.c
@@ -0,0 +1,201 @@
+/* linux/drivers/spi/spi_s3c64xx_gpio.c
+ *
+ * Copyright (c) 2009 Openmoko Inc.
+ * Author: Matt Hsu <matt_hsu@openmoko.org>
+ *
+ * S3C64XX GPIO-SPI driver.
+ * This driver is based on spi_s3c24xx_gpio.c
+ *
+ * Copyright (c) 2006 Ben Dooks
+ * Copyright (c) 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/spi-gpio.h>
+
+struct s3c64xx_spigpio {
+ struct spi_bitbang bitbang;
+ struct s3c64xx_spigpio_info *info;
+ struct platform_device *dev;
+};
+
+static inline struct s3c64xx_spigpio *spidev_to_sg(struct spi_device *spi)
+{
+ return spi->controller_data;
+}
+
+static inline void setsck(struct spi_device *dev, int on)
+{
+ struct s3c64xx_spigpio *sg = spidev_to_sg(dev);
+ gpio_direction_output(sg->info->pin_clk, on ? 1 : 0);
+}
+
+static inline void setmosi(struct spi_device *dev, int on)
+{
+ struct s3c64xx_spigpio *sg = spidev_to_sg(dev);
+ gpio_direction_output(sg->info->pin_mosi, on ? 1 : 0);
+}
+
+static inline u32 getmiso(struct spi_device *dev)
+{
+ struct s3c64xx_spigpio *sg = spidev_to_sg(dev);
+ return gpio_direction_input(sg->info->pin_miso) ? 1 : 0;
+}
+
+#define spidelay(x) ndelay(x)
+
+#define EXPAND_BITBANG_TXRX
+#include <linux/spi/spi_bitbang.h>
+
+static u32 s3c64xx_spigpio_txrx_mode0(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
+}
+
+static u32 s3c64xx_spigpio_txrx_mode1(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits);
+}
+
+static u32 s3c64xx_spigpio_txrx_mode2(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits);
+}
+
+static u32 s3c64xx_spigpio_txrx_mode3(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits);
+}
+static void s3c64xx_spigpio_chipselect(struct spi_device *dev, int value)
+{
+ struct s3c64xx_spigpio *sg = spidev_to_sg(dev);
+
+ if (sg->info && sg->info->chip_select)
+ (sg->info->chip_select)(sg->info, dev->chip_select, value);
+}
+
+static int s3c64xx_spigpio_probe(struct platform_device *dev)
+{
+ struct s3c64xx_spigpio_info *info;
+ struct spi_master *master;
+ struct s3c64xx_spigpio *spi;
+
+ int ret;
+ int i;
+
+ master = spi_alloc_master(&dev->dev, sizeof(struct s3c64xx_spigpio));
+ if (master == NULL) {
+ dev_err(&dev->dev, "failed to allocate spi master\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ spi = spi_master_get_devdata(master);
+
+ /* copy in the platform data */
+ info = spi->info = dev->dev.platform_data;
+
+ master->num_chipselect = info->num_chipselect;
+
+ /* setup spi bitbang adaptor */
+ spi->bitbang.master = spi_master_get(master);
+ spi->bitbang.master->bus_num = info->bus_num;
+
+ spi->bitbang.chipselect = s3c64xx_spigpio_chipselect;
+
+ spi->bitbang.txrx_word[SPI_MODE_0] = s3c64xx_spigpio_txrx_mode0;
+ spi->bitbang.txrx_word[SPI_MODE_1] = s3c64xx_spigpio_txrx_mode1;
+ spi->bitbang.txrx_word[SPI_MODE_2] = s3c64xx_spigpio_txrx_mode2;
+ spi->bitbang.txrx_word[SPI_MODE_3] = s3c64xx_spigpio_txrx_mode3;
+
+ /* set state of spi pins. */
+ gpio_direction_output(info->pin_clk, 0);
+ s3c_gpio_cfgpin(info->pin_clk, S3C_GPIO_OUTPUT);
+
+ ret = spi_bitbang_start(&spi->bitbang);
+ if (ret)
+ goto err_no_bitbang;
+
+ /* register the chips to go with the board */
+ for (i = 0; i < spi->info->board_size; i++) {
+ struct spi_device *spidev;
+
+ dev_info(&dev->dev, "registering %p: %s\n",
+ &spi->info->board_info[i],
+ spi->info->board_info[i].modalias);
+
+ spi->info->board_info[i].controller_data = spi;
+ spidev = spi_new_device(master, spi->info->board_info + i);
+ if (spidev)
+ spidev->max_speed_hz =
+ spi->info->board_info[i].max_speed_hz;
+ }
+
+ return 0;
+
+ err_no_bitbang:
+ spi_master_put(spi->bitbang.master);
+ err:
+ return ret;
+}
+
+static int s3c64xx_spigpio_remove(struct platform_device *dev)
+{
+ struct s3c64xx_spigpio *sp = platform_get_drvdata(dev);
+
+ spi_bitbang_stop(&sp->bitbang);
+ spi_master_put(sp->bitbang.master);
+
+ return 0;
+}
+
+#define s3c64xx_spigpio_suspend NULL
+#define s3c64xx_spigpio_resume NULL
+
+static struct platform_driver s3c64xx_spigpio_drv = {
+ .probe = s3c64xx_spigpio_probe,
+ .remove = s3c64xx_spigpio_remove,
+ .suspend = s3c64xx_spigpio_suspend,
+ .resume = s3c64xx_spigpio_resume,
+ .driver = {
+ .name = "spi_s3c64xx_gpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init s3c64xx_spigpio_init(void)
+{
+ return platform_driver_register(&s3c64xx_spigpio_drv);
+}
+
+static void __exit s3c64xx_spigpio_exit(void)
+{
+ platform_driver_unregister(&s3c64xx_spigpio_drv);
+}
+
+module_init(s3c64xx_spigpio_init);
+module_exit(s3c64xx_spigpio_exit);
+
+MODULE_DESCRIPTION("S3C64XX GPIO-SPI Driver");
+MODULE_AUTHOR("Matt Hsu, <matt_hsu@openmoko.org>");
+MODULE_LICENSE("GPLv2");
diff --git a/drivers/video/display/Kconfig b/drivers/video/display/Kconfig
index 674dc2c50fe..7350c1aaa3d 100644
--- a/drivers/video/display/Kconfig
+++ b/drivers/video/display/Kconfig
@@ -32,4 +32,12 @@ config DISPLAY_JBT6K74
The control interface is required for display operation, as it
controls power management, display timing and gamma calibration.
+config DISPLAY_L1K002
+ tristate "TP0 L1K0-02 TFT ASIC control interface"
+ depends on SPI_MASTER && SYSFS
+ help
+ The control interface of this LTPS TFT panel is based on SPI bitbang driver.
+ It controls display timing and gamma calibration. TP0 LPJ028T007A LCM uses this IC
+ as its controller in the Openmoko GTA03 GSM phone.
+
endmenu
diff --git a/drivers/video/display/Makefile b/drivers/video/display/Makefile
index 011b69ddcea..88dc958d9f0 100644
--- a/drivers/video/display/Makefile
+++ b/drivers/video/display/Makefile
@@ -4,4 +4,5 @@ display-objs := display-sysfs.o
obj-$(CONFIG_DISPLAY_SUPPORT) += display.o
obj-$(CONFIG_DISPLAY_JBT6K74) += jbt6k74.o
+obj-$(CONFIG_DISPLAY_L1K002) += l1k002.o
diff --git a/drivers/video/display/l1k002.c b/drivers/video/display/l1k002.c
new file mode 100644
index 00000000000..2115a87f21f
--- /dev/null
+++ b/drivers/video/display/l1k002.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2009 Openmoko, Inc.
+ *
+ * Author: Matt Hsu <matt_hsu@openmoko.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <linux/l1k002.h>
+
+struct l1k002_data {
+ struct spi_device *spi;
+ struct mutex lock;
+ u8 mosi_buf[2];
+ u8 reg_cache[0x40];
+};
+
+enum l1k002_regs_table {
+
+ L1K002_REG_SYNCP_SEL = 0x02,
+ L1K002_REG_VSTS = 0x03,
+ L1K002_REG_HSTS = 0x04,
+ L1K002_REG_MISC = 0x07,
+ L1K002_REG_CMDR = 0x08,
+ L1K002_REG_IN_DATA_TIMING = 0x09,
+ L1K002_REG_ENGR_OTP = 0x0b,
+ L1K002_REG_VGLS = 0x0c,
+ L1K002_REG_DISP_8_9 = 0x0d,
+ L1K002_REG_DISP_0_7 = 0x0e,
+ L1K002_REG_HTOTAL_8_10 = 0x0f,
+ L1K002_REG_HTOTAL_0_7 = 0x10,
+ L1K002_REG_WCKH = 0x20,
+ L1K002_REG_GCKH = 0x21,
+ L1K002_REG_DCKH = 0x22,
+ L1K002_REG_WENBV = 0x23,
+ L1K002_REG_DCKV = 0x25,
+ L1K002_REG_WCKV = 0x27,
+ L1K002_REG_DA_VCOM = 0x2a,
+ L1K002_REG_PVH = 0x2b,
+ L1K002_REG_NVH_NVL = 0x2c,
+ L1K002_REG_GC1 = 0x2d,
+ L1K002_REG_GC2 = 0x2e,
+ L1K002_REG_GC3 = 0x2f,
+ L1K002_REG_GC4 = 0x30,
+ L1K002_REG_GC5 = 0x31,
+ L1K002_REG_GC6 = 0x32,
+ L1K002_REG_GC7 = 0x33,
+ L1K002_REG_GC8 = 0x34,
+ L1K002_REG_GC9 = 0x35,
+ L1K002_REG_GC10 = 0x36,
+ L1K002_REG_GC11 = 0x37,
+ L1K002_REG_GC12 = 0x38,
+ L1K002_REG_GC13 = 0x39,
+ L1K002_REG_GC14 = 0x3a,
+ L1K002_REG_GC15 = 0x3b,
+};
+
+static int l1k002_reg_write(struct l1k002_data *l1k002, u8 reg, u8 data)
+{
+ int ret;
+
+ mutex_lock(&l1k002->lock);
+
+ l1k002->mosi_buf[0] = reg;
+ l1k002->mosi_buf[1] = data;
+
+ ret = spi_write(l1k002->spi, (u8 *)l1k002->mosi_buf, 2*sizeof(u8));
+ if (ret == 0)
+ l1k002->reg_cache[reg] = data;
+ else
+ dev_err(&l1k002->spi->dev, "reg spi_write ret: %d\n", ret);
+
+ mutex_unlock(&l1k002->lock);
+ return ret;
+}
+
+static int l1k002_init_reg(struct l1k002_data *l1k002)
+{
+ int ret;
+
+ /* software reset */
+ ret = l1k002_reg_write(l1k002, L1K002_REG_CMDR, 0x01);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_CMDR, 0x00);
+
+ /* setup color mode and direction */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_MISC, 0xd9);
+
+ /* dclk initial */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_SYNCP_SEL, 0x00);
+
+ /* start vertical data */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_VSTS, 0x04);
+
+ /* start horizonal data */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_HSTS, 0x14);
+
+ /* setup hsnc, vsnc, data_enable */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_IN_DATA_TIMING, 0x03);
+ /* enable engineering mode and OTP */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_ENGR_OTP, 0x18);
+
+ /* display area */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_VGLS, 0x41);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_DISP_8_9, 0x02);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_DISP_0_7, 0x80);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_HTOTAL_8_10, 0x02);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_HTOTAL_0_7, 0x08);
+
+ /* CKH pulse config */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_WCKH, 0x3c);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GCKH, 0x0c);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_DCKH, 0x10);
+
+ /* ENBV config */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_WENBV, 0x38);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_DCKV, 0x3c);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_WCKV, 0xdb);
+
+ /* driving voltage */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_DA_VCOM, 0x66);
+
+ /* gamma output voltage level */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_PVH, 0x70);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_NVH_NVL, 0x70);
+
+ /* gamma correction */
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC1, 0x15);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC2, 0xaa);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC3, 0xbf);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC4, 0x86);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC5, 0x11);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC6, 0x5e);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC7, 0xb6);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC8, 0x16);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC9, 0x4e);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC10, 0x78);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC11, 0xbf);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC12, 0xec);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC13, 0x10);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC14, 0x30);
+ ret |= l1k002_reg_write(l1k002, L1K002_REG_GC15, 0xff);
+
+ ret |= l1k002_reg_write(l1k002, 0x07, 0xc9);
+
+ if (ret == 0)
+ dev_info(&l1k002->spi->dev, "initialize OK \n");
+ else
+ dev_err(&l1k002->spi->dev, "initialize failed ret: %d\n", ret);
+ return ret;
+}
+
+static int l1k002_probe(struct spi_device *spi)
+{
+ int ret;
+ struct l1k002_data *l1k002;
+ struct l1k002_platform_data *l1k002_pdata = spi->dev.platform_data;
+
+ if (l1k002_pdata == NULL) {
+ dev_err(&spi->dev,
+ "no platform data available \n");
+ return -EINVAL;
+ }
+
+ spi->mode = SPI_CPOL | SPI_CPHA;
+ spi->bits_per_word = 8;
+
+ ret = spi_setup(spi);
+ if (ret < 0) {
+ dev_err(&spi->dev,
+ "error during spi_setup of l1k002 driver\n");
+ return ret;
+ }
+
+ l1k002 = kzalloc(sizeof(*l1k002), GFP_KERNEL);
+ if (!l1k002)
+ return -ENOMEM;
+
+ l1k002->spi = spi;
+ dev_set_drvdata(&spi->dev, l1k002);
+
+ mutex_init(&l1k002->lock);
+
+ /* hard reset l1k002 */
+ (l1k002_pdata->pwr_onoff)(1);
+
+ ret = l1k002_init_reg(l1k002);
+ if (ret)
+ goto err_free;
+
+ /* FIXME: sysfs should be added here */
+
+ return 0;
+
+err_free:
+ kfree(l1k002);
+ return ret;
+}
+
+static int __devexit l1k002_remove(struct spi_device *spi)
+{
+ struct l1k002 *l1k002 = dev_get_drvdata(&spi->dev);
+
+ dev_set_drvdata(&spi->dev, NULL);
+ kfree(l1k002);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int l1k002_suspend(struct spi_device *spi, pm_message_t state)
+{
+ struct l1k002_platform_data *l1k002_pdata = spi->dev.platform_data;
+
+ /* l1k002 doesn't have sleep mode
+ * it should be powered down as entering suspend state
+ */
+ (l1k002_pdata->pwr_onoff)(0);
+ return 0;
+}
+
+static int l1k002_resume(struct spi_device *spi)
+{
+ struct l1k002_platform_data *l1k002_pdata = spi->dev.platform_data;
+ struct l1k002 *l1k002 = dev_get_drvdata(&spi->dev);
+
+ (l1k002_pdata->pwr_onoff)(1);
+ return l1k002_init_reg(l1k002);
+}
+#else
+#define l1k002_suspend NULL
+#define l1k002_resume NULL
+#endif
+
+static struct spi_driver l1k002_driver = {
+ .driver = {
+ .name = "l1k002",
+ .owner = THIS_MODULE,
+ },
+
+ .probe = l1k002_probe,
+ .remove = __devexit_p(l1k002_remove),
+ .suspend = l1k002_suspend,
+ .resume = l1k002_resume,
+};
+
+static int __init l1k002_init(void)
+{
+ return spi_register_driver(&l1k002_driver);
+}
+
+static void __exit l1k002_exit(void)
+{
+ spi_unregister_driver(&l1k002_driver);
+}
+
+MODULE_AUTHOR("Matt Hsu <matt_hsu@openmoko.org>");
+MODULE_LICENSE("GPL v2");
+
+module_init(l1k002_init);
+module_exit(l1k002_exit);
diff --git a/include/linux/l1k002.h b/include/linux/l1k002.h
new file mode 100644
index 00000000000..54034c31922
--- /dev/null
+++ b/include/linux/l1k002.h
@@ -0,0 +1,8 @@
+#ifndef __LINUX_L1K002_H_
+#define __LINUX_L1K002_H_
+
+struct l1k002_platform_data {
+ void (*pwr_onoff)(int level);
+};
+
+#endif /* __LINUX_L1K002_H_ */