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-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c17
-rw-r--r--arch/arm/mach-omap1/board-osk.c18
-rw-r--r--arch/arm/mach-omap1/fpga.c10
-rw-r--r--arch/arm/mach-omap1/mcbsp.c280
-rw-r--r--arch/arm/mach-omap1/pm.c7
-rw-r--r--arch/arm/mach-omap1/sram.S57
7 files changed, 368 insertions, 25 deletions
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index c06f5254c0f..1bda8f5d754 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,9 @@
#
# Common support
-obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
+obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
+
+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index bcb984f2300..3f39e0e79c9 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/clk.h>
@@ -202,7 +203,7 @@ static struct omap_board_config_kernel nokia770_config[] __initdata = {
#define AMPLIFIER_CTRL_GPIO 58
static struct clk *dspxor_ck;
-static DECLARE_MUTEX(audio_pwr_sem);
+static DEFINE_MUTEX(audio_pwr_lock);
/*
* audio_pwr_state
* +--+-------------------------+---------------------------------------+
@@ -218,7 +219,7 @@ static DECLARE_MUTEX(audio_pwr_sem);
static int audio_pwr_state = -1;
/*
- * audio_pwr_up / down should be called under audio_pwr_sem
+ * audio_pwr_up / down should be called under audio_pwr_lock
*/
static void nokia770_audio_pwr_up(void)
{
@@ -237,11 +238,11 @@ static void nokia770_audio_pwr_up(void)
static void codec_delayed_power_down(struct work_struct *work)
{
- down(&audio_pwr_sem);
+ mutex_lock(&audio_pwr_lock);
if (audio_pwr_state == -1)
aic23_power_down();
clk_disable(dspxor_ck);
- up(&audio_pwr_sem);
+ mutex_unlock(&audio_pwr_lock);
}
static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
@@ -258,19 +259,19 @@ static void nokia770_audio_pwr_down(void)
static int
nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
{
- down(&audio_pwr_sem);
+ mutex_lock(&audio_pwr_lock);
if (audio_pwr_state == -1)
nokia770_audio_pwr_up();
/* force audio_pwr_state = 0, even if it was 1. */
audio_pwr_state = 0;
- up(&audio_pwr_sem);
+ mutex_unlock(&audio_pwr_lock);
return 0;
}
static int
nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
{
- down(&audio_pwr_sem);
+ mutex_lock(&audio_pwr_lock);
switch (stage) {
case 1:
if (audio_pwr_state == 0)
@@ -283,7 +284,7 @@ nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
}
break;
}
- up(&audio_pwr_sem);
+ mutex_unlock(&audio_pwr_lock);
return 0;
}
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index a66505f58b1..845c66371ca 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -267,13 +267,17 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
static void __init osk_init_smc91x(void)
{
+ u32 l;
+
if ((gpio_request(0, "smc_irq")) < 0) {
printk("Error requesting gpio 0 for smc91x irq\n");
return;
}
/* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
- EMIFS_CCS(1) |= 0x3;
+ l = omap_readl(EMIFS_CCS(1));
+ l |= 0x3;
+ omap_writel(l, EMIFS_CCS(1));
}
static void __init osk_init_cf(void)
@@ -526,20 +530,26 @@ static void __init osk_mistral_init(void) { }
static void __init osk_init(void)
{
+ u32 l;
+
/* Workaround for wrong CS3 (NOR flash) timing
* There are some U-Boot versions out there which configure
* wrong CS3 memory timings. This mainly leads to CRC
* or similar errors if you use NOR flash (e.g. with JFFS2)
*/
- if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
- EMIFS_CCS(3) = EMIFS_CS3_VAL;
+ l = omap_readl(EMIFS_CCS(3));
+ if (l != EMIFS_CS3_VAL)
+ omap_writel(EMIFS_CS3_VAL, EMIFS_CCS(3));
osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
osk_flash_resource.end += SZ_32M - 1;
platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
omap_board_config = osk_config;
omap_board_config_size = ARRAY_SIZE(osk_config);
- USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l |= (3 << 1);
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
/* irq for tps65010 chip */
/* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 30e18810904..0cf62ef5ecb 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -32,7 +32,7 @@
static void fpga_mask_irq(unsigned int irq)
{
- irq -= OMAP1510_IH_FPGA_BASE;
+ irq -= OMAP_FPGA_IRQ_BASE;
if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq)
static void fpga_unmask_irq(unsigned int irq)
{
- irq -= OMAP1510_IH_FPGA_BASE;
+ irq -= OMAP_FPGA_IRQ_BASE;
if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
@@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
if (!stat)
return;
- for (fpga_irq = OMAP1510_IH_FPGA_BASE;
- (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
+ for (fpga_irq = OMAP_FPGA_IRQ_BASE;
+ (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
fpga_irq++, stat >>= 1) {
if (stat & 1) {
d = irq_desc + fpga_irq;
@@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void)
__raw_writeb(0, OMAP1510_FPGA_IMR_HI);
__raw_writeb(0, INNOVATOR_FPGA_IMR2);
- for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
+ for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
if (i == OMAP1510_INT_FPGA_TS) {
/*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
new file mode 100644
index 00000000000..2d2c2522b04
--- /dev/null
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -0,0 +1,280 @@
+/*
+ * linux/arch/arm/mach-omap1/mcbsp.c
+ *
+ * Copyright (C) 2008 Instituto Nokia de Tecnologia
+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mcbsp.h>
+#include <asm/arch/dsp_common.h>
+
+#define DPS_RSTCT2_PER_EN (1 << 0)
+#define DSP_RSTCT2_WD_PER_EN (1 << 1)
+
+struct mcbsp_internal_clk {
+ struct clk clk;
+ struct clk **childs;
+ int n_childs;
+};
+
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
+static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{
+ const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
+ int i;
+
+ mclk->n_childs = ARRAY_SIZE(clk_names);
+ mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
+ GFP_KERNEL);
+
+ for (i = 0; i < mclk->n_childs; i++) {
+ /* We fake a platform device to get correct device id */
+ struct platform_device pdev;
+
+ pdev.dev.bus = &platform_bus_type;
+ pdev.id = mclk->clk.id;
+ mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
+ if (IS_ERR(mclk->childs[i]))
+ printk(KERN_ERR "Could not get clock %s (%d).\n",
+ clk_names[i], mclk->clk.id);
+ }
+}
+
+static int omap_mcbsp_clk_enable(struct clk *clk)
+{
+ struct mcbsp_internal_clk *mclk = container_of(clk,
+ struct mcbsp_internal_clk, clk);
+ int i;
+
+ for (i = 0; i < mclk->n_childs; i++)
+ clk_enable(mclk->childs[i]);
+ return 0;
+}
+
+static void omap_mcbsp_clk_disable(struct clk *clk)
+{
+ struct mcbsp_internal_clk *mclk = container_of(clk,
+ struct mcbsp_internal_clk, clk);
+ int i;
+
+ for (i = 0; i < mclk->n_childs; i++)
+ clk_disable(mclk->childs[i]);
+}
+
+static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
+ {
+ .clk = {
+ .name = "mcbsp_clk",
+ .id = 1,
+ .enable = omap_mcbsp_clk_enable,
+ .disable = omap_mcbsp_clk_disable,
+ },
+ },
+ {
+ .clk = {
+ .name = "mcbsp_clk",
+ .id = 3,
+ .enable = omap_mcbsp_clk_enable,
+ .disable = omap_mcbsp_clk_disable,
+ },
+ },
+};
+
+#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
+#else
+#define omap_mcbsp_clks_size 0
+static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
+static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{ }
+#endif
+
+static int omap1_mcbsp_check(unsigned int id)
+{
+ /* REVISIT: Check correctly for number of registered McBSPs */
+ if (cpu_is_omap730()) {
+ if (id > OMAP_MAX_MCBSP_COUNT - 2) {
+ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+ id + 1);
+ return -ENODEV;
+ }
+ return 0;
+ }
+
+ if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+ if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+ id + 1);
+ return -ENODEV;
+ }
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+static void omap1_mcbsp_request(unsigned int id)
+{
+ /*
+ * On 1510, 1610 and 1710, McBSP1 and McBSP3
+ * are DSP public peripherals.
+ */
+ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+ omap_dsp_request_mem();
+ /*
+ * DSP external peripheral reset
+ * FIXME: This should be moved to dsp code
+ */
+ __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
+ DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
+ }
+}
+
+static void omap1_mcbsp_free(unsigned int id)
+{
+ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+ omap_dsp_release_mem();
+}
+
+static struct omap_mcbsp_ops omap1_mcbsp_ops = {
+ .check = omap1_mcbsp_check,
+ .request = omap1_mcbsp_request,
+ .free = omap1_mcbsp_free,
+};
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
+ {
+ .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+ .rx_irq = INT_730_McBSP1RX,
+ .tx_irq = INT_730_McBSP1TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+ .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+ .rx_irq = INT_730_McBSP2RX,
+ .tx_irq = INT_730_McBSP2TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+};
+#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
+#else
+#define omap730_mcbsp_pdata NULL
+#define OMAP730_MCBSP_PDATA_SZ 0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP15XX
+static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
+ {
+ .virt_base = OMAP1510_MCBSP1_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+ .rx_irq = INT_McBSP1RX,
+ .tx_irq = INT_McBSP1TX,
+ .ops = &omap1_mcbsp_ops,
+ .clk_name = "mcbsp_clk",
+ },
+ {
+ .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+ .rx_irq = INT_1510_SPI_RX,
+ .tx_irq = INT_1510_SPI_TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+ .virt_base = OMAP1510_MCBSP3_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+ .rx_irq = INT_McBSP3RX,
+ .tx_irq = INT_McBSP3TX,
+ .ops = &omap1_mcbsp_ops,
+ .clk_name = "mcbsp_clk",
+ },
+};
+#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
+#else
+#define omap15xx_mcbsp_pdata NULL
+#define OMAP15XX_MCBSP_PDATA_SZ 0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
+ {
+ .virt_base = OMAP1610_MCBSP1_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+ .rx_irq = INT_McBSP1RX,
+ .tx_irq = INT_McBSP1TX,
+ .ops = &omap1_mcbsp_ops,
+ .clk_name = "mcbsp_clk",
+ },
+ {
+ .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+ .rx_irq = INT_1610_McBSP2_RX,
+ .tx_irq = INT_1610_McBSP2_TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+ .virt_base = OMAP1610_MCBSP3_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+ .rx_irq = INT_McBSP3RX,
+ .tx_irq = INT_McBSP3TX,
+ .ops = &omap1_mcbsp_ops,
+ .clk_name = "mcbsp_clk",
+ },
+};
+#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
+#else
+#define omap16xx_mcbsp_pdata NULL
+#define OMAP16XX_MCBSP_PDATA_SZ 0
+#endif
+
+int __init omap1_mcbsp_init(void)
+{
+ int i;
+
+ for (i = 0; i < omap_mcbsp_clks_size; i++) {
+ if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+ omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
+ clk_register(&omap_mcbsp_clks[i].clk);
+ }
+ }
+
+ if (cpu_is_omap730())
+ omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
+ OMAP730_MCBSP_PDATA_SZ);
+
+ if (cpu_is_omap15xx())
+ omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
+ OMAP15XX_MCBSP_PDATA_SZ);
+
+ if (cpu_is_omap16xx())
+ omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
+ OMAP16XX_MCBSP_PDATA_SZ);
+
+ return omap_mcbsp_init();
+}
+
+arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index e6c64e10b7e..742f79e73bd 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -116,13 +116,6 @@ void omap_pm_idle(void)
return;
}
- /*
- * Since an interrupt may set up a timer, we don't want to
- * reprogram the hardware timer with interrupts enabled.
- * Re-enable interrupts only after returning from idle.
- */
- timer_dyn_reprogram();
-
#ifdef CONFIG_OMAP_MPU_TIMER
#warning Enable 32kHz OS timer in order to allow sleep states in idle
use_idlect1 = use_idlect1 & ~(1 << 9);
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
new file mode 100644
index 00000000000..126d252062d
--- /dev/null
+++ b/arch/arm/mach-omap1/sram.S
@@ -0,0 +1,57 @@
+/*
+ * linux/arch/arm/plat-omap/sram-fn.S
+ *
+ * Functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/hardware.h>
+
+ .text
+
+/*
+ * Reprograms ULPD and CKCTL.
+ */
+ENTRY(omap1_sram_reprogram_clock)
+ stmfd sp!, {r0 - r12, lr} @ save registers on stack
+
+ mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
+ orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000
+ orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00
+
+ mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
+ orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
+ orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
+
+ tst r0, #1 << 4 @ want lock mode?
+ beq newck @ nope
+ bic r0, r0, #1 << 4 @ else clear lock bit
+ strh r0, [r2] @ set dpll into bypass mode
+ orr r0, r0, #1 << 4 @ set lock bit again
+
+newck:
+ strh r1, [r3] @ write new ckctl value
+ strh r0, [r2] @ write new dpll value
+
+ mov r4, #0x0700 @ let the clocks settle
+ orr r4, r4, #0x00ff
+delay: sub r4, r4, #1
+ cmp r4, #0
+ bne delay
+
+lock: ldrh r4, [r2], #0 @ read back dpll value
+ tst r0, #1 << 4 @ want lock mode?
+ beq out @ nope
+ tst r4, #1 << 0 @ dpll rate locked?
+ beq lock @ try again
+
+out:
+ ldmfd sp!, {r0 - r12, pc} @ restore regs and return
+ENTRY(omap1_sram_reprogram_clock_sz)
+ .word . - omap1_sram_reprogram_clock