diff options
Diffstat (limited to 'arch/arm/mach-omap2/pm34xx.c')
| -rw-r--r-- | arch/arm/mach-omap2/pm34xx.c | 47 |
1 files changed, 26 insertions, 21 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index c6cc809afb7..910a7acf542 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -26,6 +26,7 @@ #include <linux/err.h> #include <linux/gpio.h> #include <linux/clk.h> +#include <linux/delay.h> #include <plat/sram.h> #include <plat/clockdomain.h> @@ -126,7 +127,15 @@ static void omap3_core_save_context(void) /* wait for the save to complete */ while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) & PADCONF_SAVE_DONE)) - ; + udelay(1); + + /* + * Force write last pad into memory, as this can fail in some + * cases according to erratas 1.157, 1.185 + */ + omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), + OMAP343X_CONTROL_MEM_WKUP + 0x2a0); + /* Save the Interrupt controller context */ omap_intc_save_context(); /* Save the GPMC context */ @@ -392,6 +401,7 @@ void omap_sram_idle(void) prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } + omap3_intc_prepare_idle(); /* * On EMU/HS devices ROM code restores a SRDC value @@ -438,6 +448,7 @@ void omap_sram_idle(void) OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); } + omap3_intc_resume_idle(); /* PER */ if (per_next_state < PWRDM_POWER_ON) { @@ -578,6 +589,8 @@ static int omap3_pm_suspend(void) } omap_uart_prepare_suspend(); + omap3_intc_suspend(); + omap_sram_idle(); restore: @@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); } + omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); + /* * Set all plls to autoidle. This is needed until autoidle is * enabled by clockfw @@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void) prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); + /* Enable PM_WKEN to support DSS LPR */ + prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, + OMAP3430_DSS_MOD, PM_WKEN); + /* Enable wakeups in PER */ prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | - OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, + OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | + OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | + OMAP3430_EN_MCBSP4, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | - OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, + OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | + OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | + OMAP3430_EN_MCBSP4, OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); /* Don't attach IVA interrupts */ @@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void) /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - /* Don't attach IVA interrupts */ - prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); - - /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); - - /* Clear any pending PRCM interrupts */ - prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - omap3_iva_idle(); omap3_d2d_idle(); } |