diff options
Diffstat (limited to 'arch/arm/mach-sa1100')
-rw-r--r-- | arch/arm/mach-sa1100/generic.c | 15 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/h3600.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/irq.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/jornada720.c | 229 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/neponset.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/time.c | 7 |
6 files changed, 230 insertions, 43 deletions
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 4575f316e14..e510295c258 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -20,6 +20,7 @@ #include <linux/platform_device.h> #include <asm/div64.h> +#include <asm/cnt32_to_63.h> #include <asm/hardware.h> #include <asm/system.h> #include <asm/pgtable.h> @@ -118,15 +119,21 @@ EXPORT_SYMBOL(cpufreq_get); /* * This is the SA11x0 sched_clock implementation. This has - * a resolution of 271ns, and a maximum value of 1165s. + * a resolution of 271ns, and a maximum value of 32025597s (370 days). + * + * The return value is guaranteed to be monotonic in that range as + * long as there is always less than 582 seconds between successive + * calls to this function. + * * ( * 1E9 / 3686400 => * 78125 / 288) */ unsigned long long sched_clock(void) { - unsigned long long v; + unsigned long long v = cnt32_to_63(OSCR); - v = (unsigned long long)OSCR * 78125; - do_div(v, 288); + /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ + v *= 78125<<1; + do_div(v, 288<<1); return v; } diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index fa6dc71bd6a..b034ad69a32 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c @@ -702,7 +702,7 @@ static u32 gpio_irq_mask[] = { GPIO2_SD_CON_SLT, }; -static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc) +static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc) { int i; @@ -719,14 +719,14 @@ static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc) if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq); for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) if (irq & kpio_irq_mask[j]) - do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); + handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); /* GPIO2 */ irq = H3800_ASIC2_GPIINTFLAG; if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq); for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) if (irq & gpio_irq_mask[j]) - do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); + handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); } if (i >= MAX_ASIC_ISR_LOOPS) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index f4c6322ca33..5642aeca079 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -110,7 +110,7 @@ static struct irq_chip sa1100_low_gpio_chip = { * and call the handler. */ static void -sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc) +sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) { unsigned int mask; @@ -327,19 +327,19 @@ void __init sa1100_init_irq(void) for (irq = 0; irq <= 10; irq++) { set_irq_chip(irq, &sa1100_low_gpio_chip); - set_irq_handler(irq, do_edge_IRQ); + set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = 12; irq <= 31; irq++) { set_irq_chip(irq, &sa1100_normal_chip); - set_irq_handler(irq, do_level_IRQ); + set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } for (irq = 32; irq <= 48; irq++) { set_irq_chip(irq, &sa1100_high_gpio_chip); - set_irq_handler(irq, do_edge_IRQ); + set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 17f5a43acdb..54ecdaa373d 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c @@ -1,5 +1,15 @@ /* * linux/arch/arm/mach-sa1100/jornada720.c + * + * HP Jornada720 init code + * + * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl> + * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * */ #include <linux/init.h> @@ -10,13 +20,13 @@ #include <linux/ioport.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <video/s1d13xxxfb.h> #include <asm/hardware.h> #include <asm/hardware/sa1111.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <asm/setup.h> - #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> @@ -24,13 +34,170 @@ #include "generic.h" +/* + * HP Documentation referred in this file: + * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt + */ + +/* line 110 of HP's doc */ +#define TUCR_VAL 0x20000400 + +/* memory space (line 52 of HP's doc) */ +#define SA1111REGSTART 0x40000000 +#define SA1111REGLEN 0x00001fff +#define EPSONREGSTART 0x48000000 +#define EPSONREGLEN 0x00100000 +#define EPSONFBSTART 0x48200000 +/* 512kB framebuffer */ +#define EPSONFBLEN 512*1024 + +static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = { + /* line 344 of HP's doc */ + {0x0001,0x00}, // Miscellaneous Register + {0x01FC,0x00}, // Display Mode Register + {0x0004,0x00}, // General IO Pins Configuration Register 0 + {0x0005,0x00}, // General IO Pins Configuration Register 1 + {0x0008,0x00}, // General IO Pins Control Register 0 + {0x0009,0x00}, // General IO Pins Control Register 1 + {0x0010,0x01}, // Memory Clock Configuration Register + {0x0014,0x11}, // LCD Pixel Clock Configuration Register + {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register + {0x001C,0x01}, // MediaPlug Clock Configuration Register + {0x001E,0x01}, // CPU To Memory Wait State Select Register + {0x0020,0x00}, // Memory Configuration Register + {0x0021,0x45}, // DRAM Refresh Rate Register + {0x002A,0x01}, // DRAM Timings Control Register 0 + {0x002B,0x03}, // DRAM Timings Control Register 1 + {0x0030,0x1c}, // Panel Type Register + {0x0031,0x00}, // MOD Rate Register + {0x0032,0x4F}, // LCD Horizontal Display Width Register + {0x0034,0x07}, // LCD Horizontal Non-Display Period Register + {0x0035,0x01}, // TFT FPLINE Start Position Register + {0x0036,0x0B}, // TFT FPLINE Pulse Width Register + {0x0038,0xEF}, // LCD Vertical Display Height Register 0 + {0x0039,0x00}, // LCD Vertical Display Height Register 1 + {0x003A,0x13}, // LCD Vertical Non-Display Period Register + {0x003B,0x0B}, // TFT FPFRAME Start Position Register + {0x003C,0x01}, // TFT FPFRAME Pulse Width Register + {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) + {0x0041,0x00}, // LCD Miscellaneous Register + {0x0042,0x00}, // LCD Display Start Address Register 0 + {0x0043,0x00}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + {0x0046,0x80}, // LCD Memory Address Offset Register 0 + {0x0047,0x02}, // LCD Memory Address Offset Register 1 + {0x0048,0x00}, // LCD Pixel Panning Register + {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register + {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register + {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register + {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register + {0x0053,0x01}, // CRT/TV HRTC Start Position Register + {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register + {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 + {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 + {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register + {0x0059,0x09}, // CRT/TV VRTC Start Position Register + {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register + {0x005B,0x10}, // TV Output Control Register + {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) + {0x0062,0x00}, // CRT/TV Display Start Address Register 0 + {0x0063,0x00}, // CRT/TV Display Start Address Register 1 + {0x0064,0x00}, // CRT/TV Display Start Address Register 2 + {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 + {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 + {0x0068,0x00}, // CRT/TV Pixel Panning Register + {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register + {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register + {0x0070,0x00}, // LCD Ink/Cursor Control Register + {0x0071,0x01}, // LCD Ink/Cursor Start Address Register + {0x0072,0x00}, // LCD Cursor X Position Register 0 + {0x0073,0x00}, // LCD Cursor X Position Register 1 + {0x0074,0x00}, // LCD Cursor Y Position Register 0 + {0x0075,0x00}, // LCD Cursor Y Position Register 1 + {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register + {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register + {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register + {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register + {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register + {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register + {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register + {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register + {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register + {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 + {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 + {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 + {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 + {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register + {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register + {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register + {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register + {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register + {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register + {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register + {0x0100,0x00}, // BitBlt Control Register 0 + {0x0101,0x00}, // BitBlt Control Register 1 + {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register + {0x0103,0x00}, // BitBlt Operation Register + {0x0104,0x00}, // BitBlt Source Start Address Register 0 + {0x0105,0x00}, // BitBlt Source Start Address Register 1 + {0x0106,0x00}, // BitBlt Source Start Address Register 2 + {0x0108,0x00}, // BitBlt Destination Start Address Register 0 + {0x0109,0x00}, // BitBlt Destination Start Address Register 1 + {0x010A,0x00}, // BitBlt Destination Start Address Register 2 + {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 + {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 + {0x0110,0x00}, // BitBlt Width Register 0 + {0x0111,0x00}, // BitBlt Width Register 1 + {0x0112,0x00}, // BitBlt Height Register 0 + {0x0113,0x00}, // BitBlt Height Register 1 + {0x0114,0x00}, // BitBlt Background Color Register 0 + {0x0115,0x00}, // BitBlt Background Color Register 1 + {0x0118,0x00}, // BitBlt Foreground Color Register 0 + {0x0119,0x00}, // BitBlt Foreground Color Register 1 + {0x01E0,0x00}, // Look-Up Table Mode Register + {0x01E2,0x00}, // Look-Up Table Address Register + /* not sure, wouldn't like to mess with the driver */ + {0x01E4,0x00}, // Look-Up Table Data Register + /* jornada doc says 0x00, but I trust the driver */ + {0x01F0,0x10}, // Power Save Configuration Register + {0x01F1,0x00}, // Power Save Status Register + {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register + {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) +}; + +static struct s1d13xxxfb_pdata s1d13xxxfb_data = { + .initregs = s1d13xxxfb_initregs, + .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), + .platform_init_video = NULL +}; -#define JORTUCR_VAL 0x20000400 +static struct resource s1d13xxxfb_resources[] = { + [0] = { + .start = EPSONFBSTART, + .end = EPSONFBSTART + EPSONFBLEN, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = EPSONREGSTART, + .end = EPSONREGSTART + EPSONREGLEN, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device s1d13xxxfb_device = { + .name = S1D_DEVICENAME, + .id = 0, + .dev = { + .platform_data = &s1d13xxxfb_data, + }, + .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), + .resource = s1d13xxxfb_resources, +}; static struct resource sa1111_resources[] = { [0] = { - .start = 0x40000000, - .end = 0x40001fff, + .start = SA1111REGSTART, + .end = SA1111REGSTART + SA1111REGLEN, .flags = IORESOURCE_MEM, }, [1] = { @@ -53,18 +220,32 @@ static struct platform_device sa1111_device = { .resource = sa1111_resources, }; +static struct platform_device jornada720_mcu_device = { + .name = "jornada720_mcu", + .id = -1, +}; + static struct platform_device *devices[] __initdata = { &sa1111_device, + &jornada720_mcu_device, + &s1d13xxxfb_device, }; +/* a stub for now, we theoretically cannot suspend without a flashboard */ +int pm_suspend(suspend_state_t state) +{ + return -1; +} + static int __init jornada720_init(void) { int ret = -ENODEV; if (machine_is_jornada720()) { GPDR |= GPIO_GPIO20; - TUCR = JORTUCR_VAL; /* set the oscillator out to the SA-1101 */ - + /* oscillator setup (line 116 of HP's doc) */ + TUCR = TUCR_VAL; + /* resetting SA1111 (line 118 of HP's doc) */ GPSR = GPIO_GPIO20; udelay(1); GPCR = GPIO_GPIO20; @@ -72,10 +253,6 @@ static int __init jornada720_init(void) GPSR = GPIO_GPIO20; udelay(20); - /* LDD4 is speaker, LDD3 is microphone */ - PPSR &= ~(PPC_LDD3 | PPC_LDD4); - PPDR |= PPC_LDD3 | PPC_LDD4; - ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } return ret; @@ -85,19 +262,19 @@ arch_initcall(jornada720_init); static struct map_desc jornada720_io_desc[] __initdata = { { /* Epson registers */ - .virtual = 0xf0000000, - .pfn = __phys_to_pfn(0x48000000), - .length = 0x00100000, + .virtual = 0xf0000000, + .pfn = __phys_to_pfn(EPSONREGSTART), + .length = EPSONREGLEN, .type = MT_DEVICE }, { /* Epson frame buffer */ - .virtual = 0xf1000000, - .pfn = __phys_to_pfn(0x48200000), - .length = 0x00100000, + .virtual = 0xf1000000, + .pfn = __phys_to_pfn(EPSONFBSTART), + .length = EPSONFBLEN, .type = MT_DEVICE }, { /* SA-1111 */ - .virtual = 0xf4000000, - .pfn = __phys_to_pfn(0x40000000), - .length = 0x00100000, + .virtual = 0xf4000000, + .pfn = __phys_to_pfn(SA1111REGSTART), + .length = SA1111REGLEN, .type = MT_DEVICE } }; @@ -106,7 +283,7 @@ static void __init jornada720_map_io(void) { sa1100_map_io(); iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc)); - + sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); } @@ -116,7 +293,7 @@ static struct mtd_partition jornada720_partitions[] = { .name = "JORNADA720 boot firmware", .size = 0x00040000, .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "JORNADA720 kernel", .size = 0x000c0000, @@ -139,7 +316,7 @@ static struct mtd_partition jornada720_partitions[] = { .offset = 0x00540000, }, { .name = "JORNADA720 usr local", - .size = 0, /* will expand to the end of the flash */ + .size = 0, /* will expand to the end of the flash */ .offset = 0x00d00000, } }; @@ -147,10 +324,12 @@ static struct mtd_partition jornada720_partitions[] = { static void jornada720_set_vpp(int vpp) { if (vpp) - PPSR |= 0x80; + /* enabling flash write (line 470 of HP's doc) */ + PPSR |= PPC_LDD7; else - PPSR &= ~0x80; - PPDR |= 0x80; + /* disabling flash write (line 470 of HP's doc) */ + PPSR &= ~PPC_LDD7; + PPDR |= PPC_LDD7; } static struct flash_platform_data jornada720_flash_data = { diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 354d5e91da5..075d4d1d63b 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -29,12 +29,12 @@ * is rather unfortunate. */ static void -neponset_irq_handler(unsigned int irq, struct irqdesc *desc) +neponset_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int irr; while (1) { - struct irqdesc *d; + struct irq_desc *d; /* * Acknowledge the parent IRQ. @@ -168,9 +168,9 @@ static int neponset_probe(struct platform_device *dev) * Setup other Neponset IRQs. SA1111 will be done by the * generic SA1111 code. */ - set_irq_handler(IRQ_NEPONSET_SMC9196, do_simple_IRQ); + set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); - set_irq_handler(IRQ_NEPONSET_USAR, do_simple_IRQ); + set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); /* diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 4284bd6f7a1..29c89f9eb2c 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -118,6 +118,7 @@ static struct irqaction sa1100_timer_irq = { static void __init sa1100_timer_init(void) { struct timespec tv; + unsigned long flags; set_rtc = sa1100_set_rtc; @@ -126,12 +127,12 @@ static void __init sa1100_timer_init(void) do_settimeofday(&tv); OIER = 0; /* disable any timer interrupts */ - OSCR = LATCH*2; /* push OSCR out of the way */ - OSMR0 = LATCH; /* set initial match */ OSSR = 0xf; /* clear status on all timers */ setup_irq(IRQ_OST0, &sa1100_timer_irq); + local_irq_save(flags); OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ - OSCR = 0; /* initialize free-running timer */ + OSMR0 = OSCR + LATCH; /* set initial match */ + local_irq_restore(flags); } #ifdef CONFIG_NO_IDLE_HZ |