diff options
Diffstat (limited to 'arch/arm/mm')
34 files changed, 236 insertions, 182 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c0bfb8212b7..aade2f72c92 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -197,7 +197,7 @@ config CPU_ARM940T select CPU_CP15_MPU help ARM940T is a member of the ARM9TDMI family of general- - purpose microprocessors with MPU and seperate 4KB + purpose microprocessors with MPU and separate 4KB instruction and 4KB data cases, each with a 4-word line length. @@ -333,7 +333,7 @@ config CPU_XSCALE # XScale Core Version 3 config CPU_XSC3 bool - depends on ARCH_IXP23XX + depends on ARCH_IXP23XX || ARCH_IOP13XX default y select CPU_32v5 select CPU_ABRT_EV5T @@ -580,7 +580,7 @@ config CPU_CACHE_ROUND_ROBIN config CPU_BPREDICT_DISABLE bool "Disable branch prediction" - depends on CPU_ARM1020 || CPU_V6 + depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 help Say Y here to disable branch prediction. If unsure, say N. diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c index b797217e82b..6a9c362fef5 100644 --- a/arch/arm/mm/consistent.c +++ b/arch/arm/mm/consistent.c @@ -238,7 +238,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, * x86 does not mark the pages reserved... */ SetPageReserved(page); - set_pte(pte, mk_pte(page, prot)); + set_pte_ext(pte, mk_pte(page, prot), 0); page++; pte++; off++; diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c index df1645e14b4..ded0e96d069 100644 --- a/arch/arm/mm/copypage-v4mc.c +++ b/arch/arm/mm/copypage-v4mc.c @@ -19,6 +19,7 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> +#include <asm/cacheflush.h> #include "mm.h" @@ -69,9 +70,14 @@ mc_copy_user_page(void *from, void *to) void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) { + struct page *page = virt_to_page(kfrom); + + if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) + __flush_dcache_page(page_mapping(page), page); + spin_lock(&minicache_lock); - set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); + set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); flush_tlb_kernel_page(0xffff8000); mc_copy_user_page((void *)0xffff8000, kto); diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c index 3d0d3a963d2..3adb79257f4 100644 --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c @@ -53,6 +53,10 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo { unsigned int offset = CACHE_COLOUR(vaddr); unsigned long from, to; + struct page *page = virt_to_page(kfrom); + + if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) + __flush_dcache_page(page_mapping(page), page); /* * Discard data in the kernel mapping for the new page. @@ -70,8 +74,8 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo */ spin_lock(&v6_lock); - set_pte(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL)); - set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL)); + set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL), 0); + set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL), 0); from = from_address + (offset << PAGE_SHIFT); to = to_address + (offset << PAGE_SHIFT); @@ -110,7 +114,7 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr) */ spin_lock(&v6_lock); - set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL)); + set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL), 0); flush_tlb_kernel_page(to); clear_page((void *)to); diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index 84ebe0aa379..2e455f82a4d 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c @@ -19,6 +19,7 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> +#include <asm/cacheflush.h> #include "mm.h" @@ -91,9 +92,14 @@ mc_copy_user_page(void *from, void *to) void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) { + struct page *page = virt_to_page(kfrom); + + if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) + __flush_dcache_page(page_mapping(page), page); + spin_lock(&minicache_lock); - set_pte(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); + set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); flush_tlb_kernel_page(COPYPAGE_MINICACHE); mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 7fc1b35a674..cf95c5d0ce4 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -61,7 +61,7 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address) if (pte_present(entry) && pte_val(entry) & shared_pte_mask) { flush_cache_page(vma, address, pte_pfn(entry)); pte_val(entry) &= ~shared_pte_mask; - set_pte(pte, entry); + set_pte_at(vma->vm_mm, address, pte, entry); flush_tlb_page(vma, address); ret = 1; } diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 5e658a87449..9fd6d2eafb4 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -230,7 +230,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) * If we're in an interrupt or have no user * context, we must not take the fault.. */ - if (in_interrupt() || !mm) + if (in_atomic() || !mm) goto no_context; /* diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 454205b789d..9df507d36e0 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -26,7 +26,7 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); const int zero = 0; - set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); + set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0); flush_tlb_kernel_page(to); asm( "mcrr p15, 0, %1, %0, c14\n" @@ -202,3 +202,42 @@ void flush_dcache_page(struct page *page) } } EXPORT_SYMBOL(flush_dcache_page); + +/* + * Flush an anonymous page so that users of get_user_pages() + * can safely access the data. The expected sequence is: + * + * get_user_pages() + * -> flush_anon_page + * memcpy() to/from page + * if written to page, flush_dcache_page() + */ +void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) +{ + unsigned long pfn; + + /* VIPT non-aliasing caches need do nothing */ + if (cache_is_vipt_nonaliasing()) + return; + + /* + * Write back and invalidate userspace mapping. + */ + pfn = page_to_pfn(page); + if (cache_is_vivt()) { + flush_cache_page(vma, vmaddr, pfn); + } else { + /* + * For aliasing VIPT, we can flush an alias of the + * userspace address only. + */ + flush_pfn_alias(pfn, vmaddr); + } + + /* + * Invalidate kernel mapping. No data should be contained + * in this mapping of the page. FIXME: this is overkill + * since we actually ask for a write-back and invalidate. + */ + __cpuc_flush_dcache_page(page_address(page)); +} diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 46544059279..251685fe73a 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -38,89 +38,71 @@ */ #define VM_ARM_SECTION_MAPPING 0x80000000 -static inline void -remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, - unsigned long phys_addr, pgprot_t pgprot) +static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end, + unsigned long phys_addr, pgprot_t prot) { - unsigned long end; + pte_t *pte; + + pte = pte_alloc_kernel(pmd, addr); + if (!pte) + return -ENOMEM; - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - BUG_ON(address >= end); do { if (!pte_none(*pte)) goto bad; - set_pte(pte, pfn_pte(phys_addr >> PAGE_SHIFT, pgprot)); - address += PAGE_SIZE; + set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0); phys_addr += PAGE_SIZE; - pte++; - } while (address && (address < end)); - return; + } while (pte++, addr += PAGE_SIZE, addr != end); + return 0; bad: - printk("remap_area_pte: page already exists\n"); + printk(KERN_CRIT "remap_area_pte: page already exists\n"); BUG(); } -static inline int -remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, - unsigned long phys_addr, unsigned long flags) +static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr, + unsigned long end, unsigned long phys_addr, + pgprot_t prot) { - unsigned long end; - pgprot_t pgprot; - - address &= ~PGDIR_MASK; - end = address + size; - - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; + unsigned long next; + pmd_t *pmd; + int ret = 0; - phys_addr -= address; - BUG_ON(address >= end); + pmd = pmd_alloc(&init_mm, pgd, addr); + if (!pmd) + return -ENOMEM; - pgprot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_WRITE | flags); do { - pte_t * pte = pte_alloc_kernel(pmd, address); - if (!pte) - return -ENOMEM; - remap_area_pte(pte, address, end - address, address + phys_addr, pgprot); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address && (address < end)); - return 0; + next = pmd_addr_end(addr, end); + ret = remap_area_pte(pmd, addr, next, phys_addr, prot); + if (ret) + return ret; + phys_addr += next - addr; + } while (pmd++, addr = next, addr != end); + return ret; } -static int -remap_area_pages(unsigned long start, unsigned long pfn, - unsigned long size, unsigned long flags) +static int remap_area_pages(unsigned long start, unsigned long pfn, + unsigned long size, unsigned long flags) { - unsigned long address = start; - unsigned long end = start + size; + unsigned long addr = start; + unsigned long next, end = start + size; unsigned long phys_addr = __pfn_to_phys(pfn); + pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | + L_PTE_DIRTY | L_PTE_WRITE | flags); + pgd_t *pgd; int err = 0; - pgd_t * dir; - phys_addr -= address; - dir = pgd_offset(&init_mm, address); - BUG_ON(address >= end); + BUG_ON(addr >= end); + pgd = pgd_offset_k(addr); do { - pmd_t *pmd = pmd_alloc(&init_mm, dir, address); - if (!pmd) { - err = -ENOMEM; - break; - } - if (remap_area_pmd(pmd, address, end - address, - phys_addr + address, flags)) { - err = -ENOMEM; + next = pgd_addr_end(addr, end); + err = remap_area_pmd(pgd, addr, next, phys_addr, prot); + if (err) break; - } - - address = (address + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } while (address && (address < end)); + phys_addr += next - addr; + } while (pgd++, addr = next, addr != end); return err; } @@ -310,6 +292,8 @@ __ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) return NULL; + size = PAGE_ALIGN(size); + area = get_vm_area(size, VM_IOREMAP); if (!area) return NULL; diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index bb2bc9ab6bd..a44e3097063 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -1,4 +1,7 @@ /* the upper-most page table pointer */ + +#ifdef CONFIG_MMU + extern pmd_t *top_pmd; #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) @@ -13,6 +16,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt) return pmd_off(pgd_offset_k(virt), virt); } +#endif + struct map_desc; struct meminfo; struct pglist_data; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index f866bf6b97d..655c8376f0b 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -154,6 +154,26 @@ static int __init noalign_setup(char *__unused) } __setup("noalign", noalign_setup); +#ifndef CONFIG_SMP +void adjust_cr(unsigned long mask, unsigned long set) +{ + unsigned long flags; + + mask &= ~CR_A; + + set &= mask; + + local_irq_save(flags); + + cr_no_alignment = (cr_no_alignment & ~mask) | set; + cr_alignment = (cr_alignment & ~mask) | set; + + set_cr((get_cr() & ~mask) | set); + + local_irq_restore(flags); +} +#endif + struct mem_types { unsigned int prot_pte; unsigned int prot_l1; @@ -265,7 +285,7 @@ static void __init build_mem_type_table(void) if (arch_is_coherent()) { if (cpu_is_xsc3()) { mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; - mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT; + mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; } } @@ -294,12 +314,6 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE; mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; - /* - * User pages need to be mapped with the ASID - * (iow, non-global) - */ - user_pgprot |= L_PTE_ASID; - #ifdef CONFIG_SMP /* * Mark memory with the "shared" attribute for SMP systems @@ -408,7 +422,7 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg } ptep = pte_offset_kernel(pmdp, virt); - set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot)); + set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0); } /* @@ -619,6 +633,13 @@ void __init reserve_node_zero(pg_data_t *pgdat) if (machine_is_p720t()) res_size = 0x00014000; + /* H1940 and RX3715 need to reserve this for suspend */ + + if (machine_is_h1940() || machine_is_rx3715()) { + reserve_bootmem_node(pgdat, 0x30003000, 0x1000); + reserve_bootmem_node(pgdat, 0x30081000, 0x1000); + } + #ifdef CONFIG_SA1111 /* * Because of the SA1111 DMA bug, we want to preserve our diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index d0e66424a59..05818fc0c70 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -6,10 +6,12 @@ #include <linux/module.h> #include <linux/mm.h> #include <linux/pagemap.h> +#include <linux/bootmem.h> #include <asm/cacheflush.h> #include <asm/io.h> #include <asm/page.h> +#include <asm/mach/arch.h> #include "mm.h" @@ -76,7 +78,7 @@ void __iomem *__ioremap(unsigned long phys_addr, size_t size, } EXPORT_SYMBOL(__ioremap); -void __iounmap(void __iomem *addr) +void __iounmap(volatile void __iomem *addr) { } EXPORT_SYMBOL(__iounmap); diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index 20c1b0df75f..50b9aed6000 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -57,7 +57,7 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) init_pmd = pmd_offset(init_pgd, 0); init_pte = pte_offset_map_nested(init_pmd, 0); - set_pte(new_pte, *init_pte); + set_pte_ext(new_pte, *init_pte, 0); pte_unmap_nested(init_pte); pte_unmap(new_pte); } diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 1d8316f3cec..700c04d6996 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -29,9 +29,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -397,7 +397,7 @@ ENTRY(cpu_arm1020_switch_mm) * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm1020_set_pte) +ENTRY(cpu_arm1020_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -477,7 +477,7 @@ arm1020_processor_functions: .word cpu_arm1020_do_idle .word cpu_arm1020_dcache_clean_area .word cpu_arm1020_switch_mm - .word cpu_arm1020_set_pte + .word cpu_arm1020_set_pte_ext .size arm1020_processor_functions, . - arm1020_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 89b1d6d3d7c..1cc206ab5ea 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -29,9 +29,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -381,7 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm) * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm1020e_set_pte) +ENTRY(cpu_arm1020e_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -458,7 +458,7 @@ arm1020e_processor_functions: .word cpu_arm1020e_do_idle .word cpu_arm1020e_dcache_clean_area .word cpu_arm1020e_switch_mm - .word cpu_arm1020e_set_pte + .word cpu_arm1020e_set_pte_ext .size arm1020e_processor_functions, . - arm1020e_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index a089528e6bc..aff0ea08e2f 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -18,9 +18,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -358,12 +358,12 @@ ENTRY(cpu_arm1022_switch_mm) mov pc, lr /* - * cpu_arm1022_set_pte(ptep, pte) + * cpu_arm1022_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm1022_set_pte) +ENTRY(cpu_arm1022_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -441,7 +441,7 @@ arm1022_processor_functions: .word cpu_arm1022_do_idle .word cpu_arm1022_dcache_clean_area .word cpu_arm1022_switch_mm - .word cpu_arm1022_set_pte + .word cpu_arm1022_set_pte_ext .size arm1022_processor_functions, . - arm1022_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index d6d84d92c7c..65e43a10908 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -18,9 +18,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -347,12 +347,12 @@ ENTRY(cpu_arm1026_switch_mm) mov pc, lr /* - * cpu_arm1026_set_pte(ptep, pte) + * cpu_arm1026_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm1026_set_pte) +ENTRY(cpu_arm1026_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -436,7 +436,7 @@ arm1026_processor_functions: .word cpu_arm1026_do_idle .word cpu_arm1026_dcache_clean_area .word cpu_arm1026_switch_mm - .word cpu_arm1026_set_pte + .word cpu_arm1026_set_pte_ext .size arm1026_processor_functions, . - arm1026_processor_functions .section .rodata diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 0432e480688..123a7dc7a43 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -15,9 +15,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> ENTRY(cpu_arm6_dcache_clean_area) @@ -209,14 +209,14 @@ ENTRY(cpu_arm7_switch_mm) mov pc, lr /* - * Function: arm6_7_set_pte(pte_t *ptep, pte_t pte) + * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) * Params : r0 = Address to set * : r1 = value to set * Purpose : Set a PTE and flush it out of any WB cache */ .align 5 -ENTRY(cpu_arm6_set_pte) -ENTRY(cpu_arm7_set_pte) +ENTRY(cpu_arm6_set_pte_ext) +ENTRY(cpu_arm7_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -299,7 +299,7 @@ ENTRY(arm6_processor_functions) .word cpu_arm6_do_idle .word cpu_arm6_dcache_clean_area .word cpu_arm6_switch_mm - .word cpu_arm6_set_pte + .word cpu_arm6_set_pte_ext .size arm6_processor_functions, . - arm6_processor_functions /* @@ -315,7 +315,7 @@ ENTRY(arm7_processor_functions) .word cpu_arm7_do_idle .word cpu_arm7_dcache_clean_area .word cpu_arm7_switch_mm - .word cpu_arm7_set_pte + .word cpu_arm7_set_pte_ext .size arm7_processor_functions, . - arm7_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index c2f0705bfd4..dc763be4336 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -36,9 +36,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -88,13 +88,13 @@ ENTRY(cpu_arm720_switch_mm) mov pc, lr /* - * Function: arm720_set_pte(pte_t *ptep, pte_t pte) + * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) * Params : r0 = Address to set * : r1 = value to set * Purpose : Set a PTE and flush it out of any WB cache */ .align 5 -ENTRY(cpu_arm720_set_pte) +ENTRY(cpu_arm720_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -204,7 +204,7 @@ ENTRY(arm720_processor_functions) .word cpu_arm720_do_idle .word cpu_arm720_dcache_clean_area .word cpu_arm720_switch_mm - .word cpu_arm720_set_pte + .word cpu_arm720_set_pte_ext .size arm720_processor_functions, . - arm720_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 40713818a87..7069f495cf9 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -12,9 +12,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> .text diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 22d7e3100ea..d091c257182 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -12,9 +12,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> .text diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 4adb46b3a4e..75c945ed6c4 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -28,9 +28,9 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/page.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -344,12 +344,12 @@ ENTRY(cpu_arm920_switch_mm) mov pc, lr /* - * cpu_arm920_set_pte(ptep, pte) + * cpu_arm920_set_pte(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm920_set_pte) +ENTRY(cpu_arm920_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -423,7 +423,7 @@ arm920_processor_functions: .word cpu_arm920_do_idle .word cpu_arm920_dcache_clean_area .word cpu_arm920_switch_mm - .word cpu_arm920_set_pte + .word cpu_arm920_set_pte_ext .size arm920_processor_functions, . - arm920_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 571f082f024..ffb751b877f 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -29,9 +29,9 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/page.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -348,12 +348,12 @@ ENTRY(cpu_arm922_switch_mm) mov pc, lr /* - * cpu_arm922_set_pte(ptep, pte) + * cpu_arm922_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm922_set_pte) +ENTRY(cpu_arm922_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -427,7 +427,7 @@ arm922_processor_functions: .word cpu_arm922_do_idle .word cpu_arm922_dcache_clean_area .word cpu_arm922_switch_mm - .word cpu_arm922_set_pte + .word cpu_arm922_set_pte_ext .size arm922_processor_functions, . - arm922_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 8d9a9f93b01..44c2c997819 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -52,9 +52,9 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/page.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -391,12 +391,12 @@ ENTRY(cpu_arm925_switch_mm) mov pc, lr /* - * cpu_arm925_set_pte(ptep, pte) + * cpu_arm925_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm925_set_pte) +ENTRY(cpu_arm925_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -490,7 +490,7 @@ arm925_processor_functions: .word cpu_arm925_do_idle .word cpu_arm925_dcache_clean_area .word cpu_arm925_switch_mm - .word cpu_arm925_set_pte + .word cpu_arm925_set_pte_ext .size arm925_processor_functions, . - arm925_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 44a7a652d62..5b80b6bdd0c 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -28,9 +28,9 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/page.h> #include <asm/ptrace.h> #include "proc-macros.S" @@ -348,12 +348,12 @@ ENTRY(cpu_arm926_switch_mm) mov pc, lr /* - * cpu_arm926_set_pte(ptep, pte) + * cpu_arm926_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm926_set_pte) +ENTRY(cpu_arm926_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -439,7 +439,7 @@ arm926_processor_functions: .word cpu_arm926_do_idle .word cpu_arm926_dcache_clean_area .word cpu_arm926_switch_mm - .word cpu_arm926_set_pte + .word cpu_arm926_set_pte_ext .size arm926_processor_functions, . - arm926_processor_functions .section ".rodata" @@ -480,7 +480,7 @@ __arm926_proc_info: b __arm926_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA .long cpu_arm926_name .long arm926_processor_functions .long v4wbi_tlb_fns diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 2397f4b6e15..786c593778f 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -11,9 +11,9 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */ diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index e1861756442..a60c1421d45 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -13,9 +13,9 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> /* diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 918ebf65d4f..4848eeac86b 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -12,9 +12,9 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#include <asm/procinfo.h> #include <asm/ptrace.h> .text diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index c878064e9b8..6e226e12989 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -17,7 +17,7 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> -#include <asm/procinfo.h> +#include <asm/elf.h> #include <asm/hardware.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> @@ -146,12 +146,12 @@ ENTRY(cpu_sa110_switch_mm) #endif /* - * cpu_sa110_set_pte(ptep, pte) + * cpu_sa110_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_sa110_set_pte) +ENTRY(cpu_sa110_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -222,7 +222,7 @@ ENTRY(sa110_processor_functions) .word cpu_sa110_do_idle .word cpu_sa110_dcache_clean_area .word cpu_sa110_switch_mm - .word cpu_sa110_set_pte + .word cpu_sa110_set_pte_ext .size sa110_processor_functions, . - sa110_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index b23b66a6155..9afb11d089f 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -22,7 +22,7 @@ #include <linux/init.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> -#include <asm/procinfo.h> +#include <asm/elf.h> #include <asm/hardware.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> @@ -159,12 +159,12 @@ ENTRY(cpu_sa1100_switch_mm) #endif /* - * cpu_sa1100_set_pte(ptep, pte) + * cpu_sa1100_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_sa1100_set_pte) +ENTRY(cpu_sa1100_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version @@ -237,7 +237,7 @@ ENTRY(sa1100_processor_functions) .word cpu_sa1100_do_idle .word cpu_sa1100_dcache_clean_area .word cpu_sa1100_switch_mm - .word cpu_sa1100_set_pte + .word cpu_sa1100_set_pte_ext .size sa1100_processor_functions, . - sa1100_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c index ab143557e68..9f396b4fa0b 100644 --- a/arch/arm/mm/proc-syms.c +++ b/arch/arm/mm/proc-syms.c @@ -17,7 +17,7 @@ #ifndef MULTI_CPU EXPORT_SYMBOL(cpu_dcache_clean_area); -EXPORT_SYMBOL(cpu_set_pte); +EXPORT_SYMBOL(cpu_set_pte_ext); #else EXPORT_SYMBOL(processor); #endif diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 6f72549f884..7b1843befb9 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -13,8 +13,8 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/elf.h> #include <asm/hardware/arm_scu.h> -#include <asm/procinfo.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> @@ -103,13 +103,14 @@ ENTRY(cpu_v6_switch_mm) mov pc, lr /* - * cpu_v6_set_pte(ptep, pte) + * cpu_v6_set_pte_ext(ptep, pte, ext) * * Set a level 2 translation table entry. * * - ptep - pointer to level 2 translation table entry * (hardware version is stored at -1024 bytes) * - pte - PTE value to store + * - ext - value for extended PTE bits * * Permissions: * YUWD APX AP1 AP0 SVC User @@ -121,33 +122,34 @@ ENTRY(cpu_v6_switch_mm) * 11x0 0 1 0 r/w r/o * 1111 0 1 1 r/w r/w */ -ENTRY(cpu_v6_set_pte) +ENTRY(cpu_v6_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version - bic r2, r1, #0x000003f0 - bic r2, r2, #0x00000003 - orr r2, r2, #PTE_EXT_AP0 | 2 + bic r3, r1, #0x000003f0 + bic r3, r3, #0x00000003 + orr r3, r3, r2 + orr r3, r3, #PTE_EXT_AP0 | 2 tst r1, #L_PTE_WRITE tstne r1, #L_PTE_DIRTY - orreq r2, r2, #PTE_EXT_APX + orreq r3, r3, #PTE_EXT_APX tst r1, #L_PTE_USER - orrne r2, r2, #PTE_EXT_AP1 - tstne r2, #PTE_EXT_APX - bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 + orrne r3, r3, #PTE_EXT_AP1 + tstne r3, #PTE_EXT_APX + bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 tst r1, #L_PTE_YOUNG - biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK + biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK tst r1, #L_PTE_EXEC - orreq r2, r2, #PTE_EXT_XN + orreq r3, r3, #PTE_EXT_XN tst r1, #L_PTE_PRESENT - moveq r2, #0 + moveq r3, #0 - str r2, [r0] + str r3, [r0] mcr p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr @@ -156,7 +158,7 @@ ENTRY(cpu_v6_set_pte) cpu_v6_name: - .asciz "Some Random V6 Processor" + .asciz "ARMv6-compatible processor" .align .section ".text.init", #alloc, #execinstr @@ -207,11 +209,6 @@ __v6_setup: #endif mcr p15, 0, r4, c2, c0, 1 @ load TTB1 #endif /* CONFIG_MMU */ -#ifdef CONFIG_VFP - mrc p15, 0, r0, c1, c0, 2 - orr r0, r0, #(0xf << 20) - mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP -#endif adr r5, v6_crval ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0, 0 @ read control register @@ -238,7 +235,7 @@ ENTRY(v6_processor_functions) .word cpu_v6_do_idle .word cpu_v6_dcache_clean_area .word cpu_v6_switch_mm - .word cpu_v6_set_pte + .word cpu_v6_set_pte_ext .size v6_processor_functions, . - v6_processor_functions .type cpu_arch_name, #object @@ -273,7 +270,7 @@ __v6_proc_info: b __v6_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA .long cpu_v6_name .long v6_processor_functions .long v6wbi_tlb_fns diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 4ace2d8090c..94a58455f34 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -2,7 +2,7 @@ * linux/arch/arm/mm/proc-xsc3.S * * Original Author: Matthew Gilbert - * Current Maintainer: Deepak Saxena <dsaxena@plexity.net> + * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> * * Copyright 2004 (C) Intel Corp. * Copyright 2005 (c) MontaVista Software, Inc. @@ -27,7 +27,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/procinfo.h> +#include <asm/elf.h> #include <asm/hardware.h> #include <asm/pgtable.h> #include <asm/pgtable-hwdef.h> @@ -57,11 +57,6 @@ #define L2_CACHE_ENABLE 1 /* - * Enable the Branch Target Buffer (can cause crashes, see erratum #42.) - */ -#define BTB_ENABLE 0 - -/* * This macro is used to wait for a CP15 write and is needed * when we have to ensure that the last operation to the co-pro * was completed before continuing with operation. @@ -362,17 +357,19 @@ ENTRY(cpu_xsc3_switch_mm) cpwait_ret lr, ip /* - * cpu_xsc3_set_pte(ptep, pte) + * cpu_xsc3_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out * */ .align 5 -ENTRY(cpu_xsc3_set_pte) +ENTRY(cpu_xsc3_set_pte_ext) str r1, [r0], #-2048 @ linux version - bic r2, r1, #0xdf0 @ Keep C, B, coherency bits + bic r2, r1, #0xff0 @ Keep C, B bits orr r2, r2, #PTE_TYPE_EXT @ extended page + tst r1, #L_PTE_SHARED @ Shared? + orrne r2, r2, #0x200 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY @@ -432,9 +429,7 @@ __xsc3_setup: mrc p15, 0, r0, c1, c0, 0 @ get control register bic r0, r0, r5 @ .... .... .... ..A. orr r0, r0, r6 @ .... .... .... .C.M -#if BTB_ENABLE orr r0, r0, #0x00000800 @ ..VI Z..S .... .... -#endif #if L2_CACHE_ENABLE orr r0, r0, #0x04000000 @ L2 enable #endif @@ -462,7 +457,7 @@ ENTRY(xsc3_processor_functions) .word cpu_xsc3_do_idle .word cpu_xsc3_dcache_clean_area .word cpu_xsc3_switch_mm - .word cpu_xsc3_set_pte + .word cpu_xsc3_set_pte_ext .size xsc3_processor_functions, . - xsc3_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2749c1f88d7..490e11b3423 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -23,7 +23,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/procinfo.h> +#include <asm/elf.h> #include <asm/pgtable.h> #include <asm/pgtable-hwdef.h> #include <asm/page.h> @@ -421,14 +421,14 @@ ENTRY(cpu_xscale_switch_mm) cpwait_ret lr, ip /* - * cpu_xscale_set_pte(ptep, pte) + * cpu_xscale_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out * * Errata 40: must set memory to write-through for user read-only pages. */ .align 5 -ENTRY(cpu_xscale_set_pte) +ENTRY(cpu_xscale_set_pte_ext) str r1, [r0], #-2048 @ linux version bic r2, r1, #0xff0 @@ -491,12 +491,7 @@ __xscale_setup: mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs -#ifdef CONFIG_IWMMXT - mov r0, #0 @ initially disallow access to CP0/CP1 -#else - mov r0, #1 @ Allow access to CP0 -#endif - orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde + mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde orr r0, r0, #1 << 13 @ Its undefined whether this mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes @@ -534,7 +529,7 @@ ENTRY(xscale_processor_functions) .word cpu_xscale_do_idle .word cpu_xscale_dcache_clean_area .word cpu_xscale_switch_mm - .word cpu_xscale_set_pte + .word cpu_xscale_set_pte_ext .size xscale_processor_functions, . - xscale_processor_functions .section ".rodata" @@ -909,7 +904,7 @@ __pxa270_proc_info: b __xscale_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP .long cpu_pxa270_name .long xscale_processor_functions .long v4wbi_tlb_fns |