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Diffstat (limited to 'arch/arm/plat-omap/include/mach/irqs.h')
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h61
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 17248bbf3f2..a2929ac8c68 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -125,6 +125,7 @@
#define INT_UART2 (15 + IH2_BASE)
#define INT_BT_MCSI1TX (16 + IH2_BASE)
#define INT_BT_MCSI1RX (17 + IH2_BASE)
+#define INT_SOSSI_MATCH (19 + IH2_BASE)
#define INT_USB_W2FC (20 + IH2_BASE)
#define INT_1WIRE (21 + IH2_BASE)
#define INT_OS_TIMER (22 + IH2_BASE)
@@ -176,6 +177,7 @@
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
#define INT_1610_NAND (63 + IH2_BASE)
+#define INT_1610_SHA1MD5 (91 + IH2_BASE)
/*
* OMAP-730 specific IRQ numbers for interrupt handler 2
@@ -263,12 +265,18 @@
#define INT_24XX_GPTIMER10 46
#define INT_24XX_GPTIMER11 47
#define INT_24XX_GPTIMER12 48
+#define INT_24XX_SHA1MD5 51
+#define INT_24XX_MCBSP4_IRQ_TX 54
+#define INT_24XX_MCBSP4_IRQ_RX 55
#define INT_24XX_I2C1_IRQ 56
#define INT_24XX_I2C2_IRQ 57
+#define INT_24XX_HDQ_IRQ 58
#define INT_24XX_MCBSP1_IRQ_TX 59
#define INT_24XX_MCBSP1_IRQ_RX 60
#define INT_24XX_MCBSP2_IRQ_TX 62
#define INT_24XX_MCBSP2_IRQ_RX 63
+#define INT_24XX_SPI1_IRQ 65
+#define INT_24XX_SPI2_IRQ 66
#define INT_24XX_UART1_IRQ 72
#define INT_24XX_UART2_IRQ 73
#define INT_24XX_UART3_IRQ 74
@@ -278,7 +286,60 @@
#define INT_24XX_USB_IRQ_HGEN 78
#define INT_24XX_USB_IRQ_HSOF 79
#define INT_24XX_USB_IRQ_OTG 80
+#define INT_24XX_MCBSP5_IRQ_TX 81
+#define INT_24XX_MCBSP5_IRQ_RX 82
#define INT_24XX_MMC_IRQ 83
+#define INT_24XX_MMC2_IRQ 86
+#define INT_24XX_MCBSP3_IRQ_TX 89
+#define INT_24XX_MCBSP3_IRQ_RX 90
+#define INT_24XX_SPI3_IRQ 91
+
+#define INT_243X_MCBSP2_IRQ 16
+#define INT_243X_MCBSP3_IRQ 17
+#define INT_243X_MCBSP4_IRQ 18
+#define INT_243X_MCBSP5_IRQ 19
+#define INT_243X_MCBSP1_IRQ 64
+#define INT_243X_HS_USB_MC 92
+#define INT_243X_HS_USB_DMA 93
+#define INT_243X_CARKIT_IRQ 94
+
+#define INT_34XX_BENCH_MPU_EMUL 3
+#define INT_34XX_ST_MCBSP2_IRQ 4
+#define INT_34XX_ST_MCBSP3_IRQ 5
+#define INT_34XX_SSM_ABORT_IRQ 6
+#define INT_34XX_SYS_NIRQ 7
+#define INT_34XX_D2D_FW_IRQ 8
+#define INT_34XX_PRCM_MPU_IRQ 11
+#define INT_34XX_MCBSP1_IRQ 16
+#define INT_34XX_MCBSP2_IRQ 17
+#define INT_34XX_MCBSP3_IRQ 22
+#define INT_34XX_MCBSP4_IRQ 23
+#define INT_34XX_CAM_IRQ 24
+#define INT_34XX_MCBSP5_IRQ 27
+#define INT_34XX_GPIO_BANK1 29
+#define INT_34XX_GPIO_BANK2 30
+#define INT_34XX_GPIO_BANK3 31
+#define INT_34XX_GPIO_BANK4 32
+#define INT_34XX_GPIO_BANK5 33
+#define INT_34XX_GPIO_BANK6 34
+#define INT_34XX_USIM_IRQ 35
+#define INT_34XX_WDT3_IRQ 36
+#define INT_34XX_SPI4_IRQ 48
+#define INT_34XX_SHA1MD52_IRQ 49
+#define INT_34XX_FPKA_READY_IRQ 50
+#define INT_34XX_SHA1MD51_IRQ 51
+#define INT_34XX_RNG_IRQ 52
+#define INT_34XX_I2C3_IRQ 61
+#define INT_34XX_FPKA_ERROR_IRQ 64
+#define INT_34XX_PBIAS_IRQ 75
+#define INT_34XX_OHCI_IRQ 76
+#define INT_34XX_EHCI_IRQ 77
+#define INT_34XX_TLL_IRQ 78
+#define INT_34XX_PARTHASH_IRQ 79
+#define INT_34XX_MMC3_IRQ 94
+#define INT_34XX_GPT12_IRQ 95
+
+#define INT_34XX_BENCH_MPU_EMUL 3
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
* 16 MPUIO lines */