diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/Makefile | 2 | ||||
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 162 | ||||
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 98 |
3 files changed, 262 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index a8f493f2f21..1efeda0e182 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -5,6 +5,7 @@ # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o +obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o @@ -13,6 +14,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o +clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7343.o diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c new file mode 100644 index 00000000000..805535aa505 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -0,0 +1,162 @@ +/* + * arch/sh/kernel/cpu/sh4a/clock-sh7785.c + * + * SH7785 support for the clock framework + * + * Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <asm/clock.h> +#include <asm/freq.h> +#include <asm/io.h> + +static int ifc_divisors[] = { 1, 2, 4, 6 }; +static int ufc_divisors[] = { 1, 1, 4, 6 }; +static int sfc_divisors[] = { 1, 1, 4, 6 }; +static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, + 24, 32, 36, 48, 1, 1, 1, 1 }; +static int mfc_divisors[] = { 1, 1, 4, 6 }; +static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, + 24, 32, 36, 48, 1, 1, 1, 1 }; + +static void master_clk_init(struct clk *clk) +{ + clk->rate *= 36; +} + +static struct clk_ops sh7785_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inl(FRQMR1) & 0x000f); + clk->rate = clk->parent->rate / pfc_divisors[idx]; +} + +static struct clk_ops sh7785_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); + clk->rate = clk->parent->rate / bfc_divisors[idx]; +} + +static struct clk_ops sh7785_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); + clk->rate = clk->parent->rate / ifc_divisors[idx]; +} + +static struct clk_ops sh7785_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *sh7785_clk_ops[] = { + &sh7785_master_clk_ops, + &sh7785_module_clk_ops, + &sh7785_bus_clk_ops, + &sh7785_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + if (idx < ARRAY_SIZE(sh7785_clk_ops)) + *ops = sh7785_clk_ops[idx]; +} + +static void shyway_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); + clk->rate = clk->parent->rate / sfc_divisors[idx]; +} + +static struct clk_ops sh7785_shyway_clk_ops = { + .recalc = shyway_clk_recalc, +}; + +static struct clk sh7785_shyway_clk = { + .name = "shyway_clk", + .flags = CLK_ALWAYS_ENABLED, + .ops = &sh7785_shyway_clk_ops, +}; + +static void ddr_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); + clk->rate = clk->parent->rate / mfc_divisors[idx]; +} + +static struct clk_ops sh7785_ddr_clk_ops = { + .recalc = ddr_clk_recalc, +}; + +static struct clk sh7785_ddr_clk = { + .name = "ddr_clk", + .flags = CLK_ALWAYS_ENABLED, + .ops = &sh7785_ddr_clk_ops, +}; + +static void ram_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003); + clk->rate = clk->parent->rate / ufc_divisors[idx]; +} + +static struct clk_ops sh7785_ram_clk_ops = { + .recalc = ram_clk_recalc, +}; + +static struct clk sh7785_ram_clk = { + .name = "ram_clk", + .flags = CLK_ALWAYS_ENABLED, + .ops = &sh7785_ram_clk_ops, +}; + +/* + * Additional SH7785-specific on-chip clocks that aren't already part of the + * clock framework + */ +static struct clk *sh7785_onchip_clocks[] = { + &sh7785_shyway_clk, + &sh7785_ddr_clk, + &sh7785_ram_clk, +}; + +static int __init sh7785_clk_init(void) +{ + struct clk *clk = clk_get(NULL, "master_clk"); + int i; + + for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) { + struct clk *clkp = sh7785_onchip_clocks[i]; + + clkp->parent = clk; + clk_register(clkp); + clk_enable(clkp); + } + + /* + * Now that we have the rest of the clocks registered, we need to + * force the parent clock to propagate so that these clocks will + * automatically figure out their rate. We cheat by handing the + * parent clock its current rate and forcing child propagation. + */ + clk_set_rate(clk, clk_get_rate(clk)); + + clk_put(clk); + + return 0; +} +arch_initcall(sh7785_clk_init); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c new file mode 100644 index 00000000000..c9ae6592f09 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -0,0 +1,98 @@ +/* + * SH7785 Setup + * + * Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <asm/sci.h> + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xffea0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 40, 41, 43, 42 }, + }, { + .mapbase = 0xffeb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 44, 45, 47, 46 }, + }, + + /* + * The rest of these all have multiplexed IRQs + */ + { + .mapbase = 0xffec0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 60, 60, 60, 60 }, + }, { + .mapbase = 0xffed0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 61, 61, 61, 61 }, + }, { + .mapbase = 0xffee0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 62, 62, 62, 62 }, + }, { + .mapbase = 0xffef0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 63, 63, 63, 63 }, + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct platform_device *sh7785_devices[] __initdata = { + &sci_device, +}; + +static int __init sh7785_devices_setup(void) +{ + return platform_add_devices(sh7785_devices, + ARRAY_SIZE(sh7785_devices)); +} +__initcall(sh7785_devices_setup); + +static struct intc2_data intc2_irq_table[] = { + { 28, 0, 24, 0, 0, 2 }, /* TMU0 */ + + { 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */ + { 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */ + { 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */ + { 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */ + + { 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */ + { 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */ + { 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */ + { 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */ + + { 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */ + { 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */ + { 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */ + { 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */ + { 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */ +}; + +void __init init_IRQ_intc2(void) +{ + make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table)); +} |