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-rw-r--r--drivers/gpio/glamo-gpio.c82
-rw-r--r--drivers/mfd/glamo-core.c135
-rw-r--r--drivers/mmc/host/glamo-mci.c56
-rw-r--r--drivers/video/glamo-fb.c86
4 files changed, 187 insertions, 172 deletions
diff --git a/drivers/gpio/glamo-gpio.c b/drivers/gpio/glamo-gpio.c
index 185b86b64e4..7d00bd4f98a 100644
--- a/drivers/gpio/glamo-gpio.c
+++ b/drivers/gpio/glamo-gpio.c
@@ -34,7 +34,7 @@
#define GLAMO_NR_GPIO 21
#define GLAMO_NR_GPIO_REGS DIV_ROUND_UP(GLAMO_NR_GPIO, 4)
-#define GLAMO_REG_GPIO(x) (((x) * 2) + GLAMO_REG_GPIO_GEN1)
+#define GLAMO_GPIO_REG(x) (((x) * 2) + GLAMO_GPIO_REG_GEN1)
struct glamo_gpio {
struct glamo_core *glamo;
@@ -42,12 +42,12 @@ struct glamo_gpio {
uint16_t saved_regs[GLAMO_NR_GPIO_REGS];
};
-#define REG_OF_GPIO(gpio) (GLAMO_REG_GPIO(gpio >> 2))
-#define NUM_OF_GPIO(gpio) (gpio & 0x3)
-#define DIRECTION_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 0))
-#define OUTPUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 4))
-#define INPUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 8))
-#define FUNC_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 12))
+#define GLAMO_GPIO_REG_GPIO(gpio) GLAMO_GPIO_REG(gpio >> 2)
+#define GLAMO_GPIO_BIT(gpio, offset) BIT(((gpio) & 0x3) + (offset))
+#define GLAMO_GPIO_DIRECTION_BIT(gpio) GLAMO_GPIO_BIT(gpio, 0)
+#define GLAMO_GPIO_OUTPUT_BIT(gpio) GLAMO_GPIO_BIT(gpio, 4)
+#define GLAMO_GPIO_INPUT_BIT(gpio) GLAMO_GPIO_BIT(gpio, 8)
+#define GLAMO_GPIO_FUNC_BIT(gpio) GLAMO_GPIO_BIT(gpio, 12)
static inline struct glamo_core *chip_to_glamo(struct gpio_chip *chip)
@@ -58,15 +58,15 @@ static inline struct glamo_core *chip_to_glamo(struct gpio_chip *chip)
static void glamo_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct glamo_core *glamo = chip_to_glamo(chip);
- unsigned int reg = REG_OF_GPIO(offset);
- u_int16_t tmp;
+ unsigned int reg = GLAMO_GPIO_REG_GPIO(offset);
+ uint16_t tmp;
spin_lock(&glamo->lock);
tmp = readw(glamo->base + reg);
if (value)
- tmp |= OUTPUT_BIT(offset);
+ tmp |= GLAMO_GPIO_OUTPUT_BIT(offset);
else
- tmp &= ~OUTPUT_BIT(offset);
+ tmp &= ~GLAMO_GPIO_OUTPUT_BIT(offset);
writew(tmp, glamo->base + reg);
spin_unlock(&glamo->lock);
}
@@ -74,19 +74,19 @@ static void glamo_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int glamo_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct glamo_core *glamo = chip_to_glamo(chip);
- return !!(readw(glamo->base + REG_OF_GPIO(offset)) & INPUT_BIT(offset));
+ return !!(readw(glamo->base + GLAMO_GPIO_REG_GPIO(offset)) & GLAMO_GPIO_INPUT_BIT(offset));
}
static int glamo_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct glamo_core *glamo = chip_to_glamo(chip);
- unsigned int reg = REG_OF_GPIO(offset);
- u_int16_t tmp;
+ unsigned int reg = GLAMO_GPIO_REG_GPIO(offset);
+ uint16_t tmp;
spin_lock(&glamo->lock);
tmp = readw(glamo->base + reg);
- if ((tmp & FUNC_BIT(offset)) == 0) {
- tmp |= FUNC_BIT(offset);
+ if ((tmp & GLAMO_GPIO_FUNC_BIT(offset)) == 0) {
+ tmp |= GLAMO_GPIO_FUNC_BIT(offset);
writew(tmp, glamo->base + reg);
}
spin_unlock(&glamo->lock);
@@ -97,13 +97,13 @@ static int glamo_gpio_request(struct gpio_chip *chip, unsigned offset)
static void glamo_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct glamo_core *glamo = chip_to_glamo(chip);
- unsigned int reg = REG_OF_GPIO(offset);
- u_int16_t tmp;
+ unsigned int reg = GLAMO_GPIO_REG_GPIO(offset);
+ uint16_t tmp;
spin_lock(&glamo->lock);
tmp = readw(glamo->base + reg);
- if ((tmp & FUNC_BIT(offset)) == 1) {
- tmp &= ~FUNC_BIT(offset);
+ if ((tmp & GLAMO_GPIO_FUNC_BIT(offset)) == 1) {
+ tmp &= ~GLAMO_GPIO_FUNC_BIT(offset);
writew(tmp, glamo->base + reg);
}
spin_unlock(&glamo->lock);
@@ -113,17 +113,17 @@ static int glamo_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
struct glamo_core *glamo = chip_to_glamo(chip);
- unsigned int reg = REG_OF_GPIO(offset);
- u_int16_t tmp;
+ unsigned int reg = GLAMO_GPIO_REG_GPIO(offset);
+ uint16_t tmp;
spin_lock(&glamo->lock);
tmp = readw(glamo->base + reg);
- tmp &= ~DIRECTION_BIT(offset);
+ tmp &= ~GLAMO_GPIO_DIRECTION_BIT(offset);
if (value)
- tmp |= OUTPUT_BIT(offset);
+ tmp |= GLAMO_GPIO_OUTPUT_BIT(offset);
else
- tmp &= ~OUTPUT_BIT(offset);
+ tmp &= ~GLAMO_GPIO_OUTPUT_BIT(offset);
writew(tmp, glamo->base + reg);
spin_unlock(&glamo->lock);
@@ -134,13 +134,13 @@ static int glamo_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
static int glamo_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct glamo_core *glamo = chip_to_glamo(chip);
- unsigned int reg = REG_OF_GPIO(offset);
- u_int16_t tmp;
+ unsigned int reg = GLAMO_GPIO_REG_GPIO(offset);
+ uint16_t tmp;
spin_lock(&glamo->lock);
tmp = readw(glamo->base + reg);
- if ((tmp & DIRECTION_BIT(offset)) == 0) {
- tmp |= DIRECTION_BIT(offset);
+ if ((tmp & GLAMO_GPIO_DIRECTION_BIT(offset)) == 0) {
+ tmp |= GLAMO_GPIO_DIRECTION_BIT(offset);
writew(tmp, glamo->base + reg);
}
spin_unlock(&glamo->lock);
@@ -149,17 +149,17 @@ static int glamo_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
}
static const struct __devinit gpio_chip glamo_gpio_chip = {
- .label = "glamo",
- .request = glamo_gpio_request,
- .free = glamo_gpio_free,
+ .label = "glamo",
+ .request = glamo_gpio_request,
+ .free = glamo_gpio_free,
.direction_input = glamo_gpio_direction_input,
- .get = glamo_gpio_get,
+ .get = glamo_gpio_get,
.direction_output = glamo_gpio_direction_output,
- .set = glamo_gpio_set,
- .base = -1,
- .ngpio = GLAMO_NR_GPIO,
- .can_sleep = 0,
- .owner = THIS_MODULE,
+ .set = glamo_gpio_set,
+ .base = -1,
+ .ngpio = GLAMO_NR_GPIO,
+ .can_sleep = 0,
+ .owner = THIS_MODULE,
};
static int __devinit glamo_gpio_probe(struct platform_device *pdev)
@@ -168,7 +168,7 @@ static int __devinit glamo_gpio_probe(struct platform_device *pdev)
struct glamo_gpio *glamo_gpio;
int ret;
- glamo_gpio = kzalloc(sizeof(struct glamo_gpio), GFP_KERNEL);
+ glamo_gpio = kzalloc(sizeof(*glamo_gpio), GFP_KERNEL);
if (!glamo_gpio)
return -ENOMEM;
@@ -223,7 +223,7 @@ static int glamo_gpio_suspend(struct device *dev)
spin_lock(&glamo->lock);
for (i = 0; i < GLAMO_NR_GPIO / 4; ++i)
- saved_regs[i] = readw(glamo->base + GLAMO_REG_GPIO(i));
+ saved_regs[i] = readw(glamo->base + GLAMO_GPIO_REG(i));
spin_unlock(&glamo->lock);
return 0;
@@ -238,7 +238,7 @@ static int glamo_gpio_resume(struct device *dev)
spin_lock(&glamo->lock);
for (i = 0; i < GLAMO_NR_GPIO_REGS; ++i)
- writew(saved_regs[i], glamo->base + GLAMO_REG_GPIO(i));
+ writew(saved_regs[i], glamo->base + GLAMO_GPIO_REG(i));
spin_unlock(&glamo->lock);
return 0;
}
diff --git a/drivers/mfd/glamo-core.c b/drivers/mfd/glamo-core.c
index 135856af1ee..05bc7375b3e 100644
--- a/drivers/mfd/glamo-core.c
+++ b/drivers/mfd/glamo-core.c
@@ -40,6 +40,9 @@
#include <linux/mfd/glamo-core.h>
#include <linux/io.h>
#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <asm/uaccess.h>
#include <linux/pm.h>
@@ -175,40 +178,6 @@ static inline void __reg_clear_bit(struct glamo_core *glamo,
__reg_write(glamo, reg, tmp);
}
-static void __reg_write_batch(struct glamo_core *glamo, uint16_t reg,
- uint16_t count, uint16_t *values)
-{
- uint16_t end;
- for (end = reg + count * 2; reg < end; reg += 2, ++values)
- __reg_write(glamo, reg, *values);
-}
-
-static void __reg_read_batch(struct glamo_core *glamo, uint16_t reg,
- uint16_t count, uint16_t *values)
-{
- uint16_t end;
- for (end = reg + count * 2; reg < end; reg += 2, ++values)
- *values = __reg_read(glamo, reg);
-}
-
-void glamo_reg_write_batch(struct glamo_core *glamo, uint16_t reg,
- uint16_t count, uint16_t *values)
-{
- spin_lock(&glamo->lock);
- __reg_write_batch(glamo, reg, count, values);
- spin_unlock(&glamo->lock);
-}
-EXPORT_SYMBOL(glamo_reg_write_batch);
-
-void glamo_reg_read_batch(struct glamo_core *glamo, uint16_t reg,
- uint16_t count, uint16_t *values)
-{
- spin_lock(&glamo->lock);
- __reg_read_batch(glamo, reg, count, values);
- spin_unlock(&glamo->lock);
-}
-EXPORT_SYMBOL(glamo_reg_read_batch);
-
/***********************************************************************
* resources of sibling devices
***********************************************************************/
@@ -351,52 +320,68 @@ static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
}
/*
-sysfs
+debugfs
*/
-static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
+#ifdef CONFIG_DEBUG_FS
+static ssize_t debugfs_regs_write(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
{
- struct glamo_core *glamo = dev_get_drvdata(dev);
+ struct glamo_core *glamo = ((struct seq_file *)file->private_data)->private;
+ char buf[14];
unsigned int reg;
unsigned int val;
+ int buf_size;
+
+ buf_size = min(count, sizeof(buf) - 1);
+ if (copy_from_user(buf, user_buf, buf_size))
+ return -EFAULT;
+ if (sscanf(buf, "%x %x", &reg, &val) != 2)
+ return -EFAULT;
- sscanf(buf, "%u %u", &reg, &val);
- printk(KERN_INFO"reg 0x%02x <-- 0x%04x\n",
- reg, val);
+ dev_info(&glamo->pdev->dev, "reg %#02x <-- %#04x\n", reg, val);
glamo_reg_write(glamo, reg, val);
return count;
}
-static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
- char *buf)
+static int glamo_show_regs(struct seq_file *s, void *pos)
{
- struct glamo_core *glamo = dev_get_drvdata(dev);
+ struct glamo_core *glamo = s->private;
int i, n;
- char *end = buf;
const struct reg_range *rr = reg_range;
spin_lock(&glamo->lock);
-
for (i = 0; i < ARRAY_SIZE(reg_range); ++i, ++rr) {
if (!rr->dump)
continue;
- end += sprintf(end, "\n%s\n", rr->name);
+ seq_printf(s, "\n%s\n", rr->name);
for (n = rr->start; n < rr->start + rr->count; n += 2) {
if ((n & 15) == 0)
- end += sprintf(end, "\n%04X: ", n);
- end += sprintf(end, "%04x ", __reg_read(glamo, n));
+ seq_printf(s, "\n%04X: ", n);
+ seq_printf(s, "%04x ", __reg_read(glamo, n));
}
- end += sprintf(end, "\n");
+ seq_printf(s, "\n");
}
spin_unlock(&glamo->lock);
- return end - buf;
+ return 0;
+}
+
+static int debugfs_open_file(struct inode *inode, struct file *file)
+{
+ return single_open(file, glamo_show_regs, inode->i_private);
}
-static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
+static const struct file_operations debugfs_regs_ops = {
+ .open = debugfs_open_file,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .write = debugfs_regs_write,
+ .release = single_release,
+};
struct glamo_engine_reg_set {
uint16_t reg;
@@ -404,6 +389,31 @@ struct glamo_engine_reg_set {
uint16_t mask_enabled;
};
+static void glamo_init_debugfs(struct glamo_core *glamo)
+{
+ glamo->debugfs_dir = debugfs_create_dir("glamo3362", NULL);
+ if (glamo->debugfs_dir)
+ debugfs_create_file("regs", S_IRUGO | S_IWUSR, glamo->debugfs_dir,
+ glamo, &debugfs_regs_ops);
+ else
+ dev_warn(&glamo->pdev->dev, "Failed to set up debugfs.\n");
+}
+
+static void glamo_exit_debugfs(struct glamo_core *glamo)
+{
+ if (glamo->debugfs_dir)
+ debugfs_remove_recursive(glamo->debugfs_dir);
+}
+#else
+static void glamo_init_debugfs(struct glamo_core *glamo)
+{
+}
+
+static void glamo_exit_debugfs(struct glamo_core *glamo)
+{
+}
+#endif
+
struct glamo_engine_desc {
const char *name;
uint16_t hostbus;
@@ -828,8 +838,8 @@ static const struct glamo_script glamo_init_script[] = {
* b7..b4 = 0 = no wait states on read or write
* b0 = 1 select PLL2 for Host interface, b1 = enable it
*/
- { GLAMO_REG_HOSTBUS(0), 0x0e03 /* this is replaced by script parser */ },
- { GLAMO_REG_HOSTBUS(1), 0x07ff }, /* TODO: Disable all */
+ { GLAMO_REG_HOSTBUS(1), 0x0e03 /* this is replaced by script parser */ },
+ { GLAMO_REG_HOSTBUS(2), 0x07ff }, /* TODO: Disable all */
{ GLAMO_REG_HOSTBUS(10), 0x0000 },
{ GLAMO_REG_HOSTBUS(11), 0x4000 },
{ GLAMO_REG_HOSTBUS(12), 0xf00e },
@@ -901,7 +911,7 @@ static int __devinit glamo_supported(struct glamo_core *glamo)
static int __devinit glamo_probe(struct platform_device *pdev)
{
- int ret = 0, irq, irq_base;
+ int ret = 0, n, irq, irq_base;
struct glamo_core *glamo;
struct resource *mem;
@@ -909,6 +919,9 @@ static int __devinit glamo_probe(struct platform_device *pdev)
if (!glamo)
return -ENOMEM;
+ for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
+ glamo->engine_state[n] = GLAMO_ENGINE_DISABLED;
+
spin_lock_init(&glamo->lock);
glamo->pdev = pdev;
@@ -966,12 +979,8 @@ static int __devinit glamo_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, glamo);
- /* sysfs */
- ret = device_create_file(&pdev->dev, &dev_attr_regs);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to create sysfs file\n");
- goto err_iounmap;
- }
+ /* debugfs */
+ glamo_init_debugfs(glamo);
/* init the chip with canned register set */
glamo_run_script(glamo, glamo_init_script,
@@ -1040,6 +1049,8 @@ static int __devexit glamo_remove(struct platform_device *pdev)
int irq;
int irq_base = glamo->irq_base;
+ glamo_exit_debugfs(glamo);
+
mfd_remove_devices(&pdev->dev);
disable_irq(glamo->irq);
@@ -1163,7 +1174,7 @@ static int glamo_suspend(struct device *dev)
/* take down each engine before we kill mem and pll */
for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
- if (glamo->engine_state != GLAMO_ENGINE_DISABLED)
+ if (glamo->engine_state[n] != GLAMO_ENGINE_DISABLED)
__glamo_engine_disable(glamo, n);
}
diff --git a/drivers/mmc/host/glamo-mci.c b/drivers/mmc/host/glamo-mci.c
index b2442c22b1a..f07ad094079 100644
--- a/drivers/mmc/host/glamo-mci.c
+++ b/drivers/mmc/host/glamo-mci.c
@@ -110,19 +110,19 @@ static int sd_post_power_clock = 1000000;
module_param(sd_post_power_clock, int, 0644);
-static inline void glamo_reg_write(struct glamo_mci_host *glamo,
+static inline void glamomci_reg_write(struct glamo_mci_host *glamo,
uint16_t reg, uint16_t val)
{
writew(val, glamo->mmio_base + reg);
}
-static inline uint16_t glamo_reg_read(struct glamo_mci_host *glamo,
+static inline uint16_t glamomci_reg_read(struct glamo_mci_host *glamo,
uint16_t reg)
{
return readw(glamo->mmio_base + reg);
}
-static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
+static void glamomci_reg_set_bit_mask(struct glamo_mci_host *glamo,
uint16_t reg, uint16_t mask,
uint16_t val)
{
@@ -130,24 +130,24 @@ static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
val &= mask;
- tmp = glamo_reg_read(glamo, reg);
+ tmp = glamomci_reg_read(glamo, reg);
tmp &= ~mask;
tmp |= val;
- glamo_reg_write(glamo, reg, tmp);
+ glamomci_reg_write(glamo, reg, tmp);
}
static void glamo_mci_reset(struct glamo_mci_host *host)
{
glamo_engine_reset(host->core, GLAMO_ENGINE_MMC);
- glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
+ glamomci_reg_write(host, GLAMO_REG_MMC_WDATADS1,
(uint16_t)(host->data_mem->start));
- glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
+ glamomci_reg_write(host, GLAMO_REG_MMC_WDATADS2,
(uint16_t)(host->data_mem->start >> 16));
- glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
+ glamomci_reg_write(host, GLAMO_REG_MMC_RDATADS1,
(uint16_t)(host->data_mem->start));
- glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
+ glamomci_reg_write(host, GLAMO_REG_MMC_RDATADS2,
(uint16_t)(host->data_mem->start >> 16));
}
@@ -226,7 +226,7 @@ static int glamo_mci_wait_idle(struct glamo_mci_host *host,
{
uint16_t status;
do {
- status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+ status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
} while (!(status & GLAMO_STAT1_MMC_IDLE) &&
time_is_after_jiffies(timeout));
@@ -257,7 +257,7 @@ static irqreturn_t glamo_mci_irq(int irq, void *data)
mrq = host->mrq;
cmd = mrq->cmd;
- status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+ status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
/* we ignore a data timeout report if we are also told the data came */
@@ -320,7 +320,7 @@ static void glamo_mci_read_worker(struct work_struct *work)
* But the question is: what happens between the moment
* the error occurs, and the moment the IRQ handler handles it?
*/
- status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+ status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
cmd->error = -ETIMEDOUT;
@@ -332,7 +332,7 @@ static void glamo_mci_read_worker(struct work_struct *work)
return;
}
- blocks_ready = glamo_reg_read(host, GLAMO_REG_MMC_RB_BLKCNT);
+ blocks_ready = glamomci_reg_read(host, GLAMO_REG_MMC_RB_BLKCNT);
data_ready = blocks_ready * cmd->data->blksz;
if (data_ready == data_read)
@@ -364,7 +364,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
int triggers_int = 1;
/* if we can't do it, reject as busy */
- if (!(glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
+ if (!(glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
GLAMO_STAT1_MMC_IDLE)) {
cmd->error = -EBUSY;
return;
@@ -379,9 +379,9 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01;
/* issue the wire-order array including CRC in register order */
- glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
- glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
- glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
+ glamomci_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
+ glamomci_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
+ glamomci_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
/* command index toggle */
fire |= (host->request_counter & 1) << 12;
@@ -478,10 +478,10 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
host->mrq = cmd->mrq;
/* always largest timeout */
- glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
+ glamomci_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
/* Generate interrupt on txfer */
- glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
+ glamomci_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
0x0800 |
GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
GLAMO_BASIC_MMC_EN_COMPL_INT |
@@ -490,7 +490,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
/* send the command out on the wire */
/* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
- glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
+ glamomci_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
/* we are deselecting card? because it isn't going to ack then... */
if ((cmd->opcode == 7) && (cmd->arg == 0))
@@ -501,7 +501,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
* -- we don't get interrupts unless there is a bulk rx
*/
do
- status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+ status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
(!(status & (GLAMO_STAT1_MMC_RB_RRDY |
GLAMO_STAT1_MMC_RTOUT |
@@ -547,8 +547,8 @@ static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
struct mmc_data *data)
{
/* set up the block info */
- glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
- glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
+ glamomci_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
+ glamomci_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
data->bytes_xfered = 0;
@@ -678,7 +678,7 @@ static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
if (sd_drive > 3)
sd_drive = 3;
- glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
+ glamomci_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xc0,
bus_width | sd_drive << 6);
@@ -812,6 +812,10 @@ static int glamo_mci_probe(struct platform_device *pdev)
mmc->caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED |
MMC_CAP_SD_HIGHSPEED;
+
+ if (host->pdata->nonremovable)
+ mmc->caps |= MMC_CAP_NONREMOVABLE;
+
mmc->f_min = host->clk_rate / 256;
mmc->f_max = sd_max_clk;
@@ -930,10 +934,10 @@ static int glamo_mci_resume(struct device *dev)
glamo_mci_reset(host);
mdelay(10);
- ret = mmc_resume_host(host->mmc);
-
enable_irq(host->irq);
+ ret = mmc_resume_host(host->mmc);
+
mmc_host_lazy_disable(host->mmc);
return ret;
diff --git a/drivers/video/glamo-fb.c b/drivers/video/glamo-fb.c
index 517cc5c711e..3f8ec8d466a 100644
--- a/drivers/video/glamo-fb.c
+++ b/drivers/video/glamo-fb.c
@@ -95,12 +95,12 @@ static void glamo_output_disable(struct glamofb_handle *gfb)
}
-static inline int reg_read(struct glamofb_handle *glamo, uint16_t reg)
+static inline int glamofb_reg_read(struct glamofb_handle *glamo, uint16_t reg)
{
return readw(glamo->base + reg);
}
-static inline void reg_write(struct glamofb_handle *glamo, uint16_t reg,
+static inline void glamofb_reg_write(struct glamofb_handle *glamo, uint16_t reg,
uint16_t val)
{
writew(val, glamo->base + reg);
@@ -146,7 +146,7 @@ static int glamofb_run_script(struct glamofb_handle *glamo,
else if (line->reg == 0xfffe)
msleep(line->val);
else
- reg_write(glamo, script[i].reg, script[i].val);
+ glamofb_reg_write(glamo, script[i].reg, script[i].val);
}
return 0;
@@ -166,7 +166,7 @@ static int glamofb_check_var(struct fb_var_screeninfo *var,
/* FIXME: set rgb positions */
switch (var->bits_per_pixel) {
case 16:
- switch (reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
+ switch (glamofb_reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
case GLAMO_LCD_SRC_RGB565:
var->red.offset = 11;
var->green.offset = 5;
@@ -208,17 +208,17 @@ static int glamofb_check_var(struct fb_var_screeninfo *var,
return 0;
}
-static void reg_set_bit_mask(struct glamofb_handle *glamo, uint16_t reg,
+static void glamofb_reg_set_bit_mask(struct glamofb_handle *glamo, uint16_t reg,
uint16_t mask, uint16_t val)
{
uint16_t tmp;
val &= mask;
- tmp = reg_read(glamo, reg);
+ tmp = glamofb_reg_read(glamo, reg);
tmp &= ~mask;
tmp |= val;
- reg_write(glamo, reg, tmp);
+ glamofb_reg_write(glamo, reg, tmp);
}
#define GLAMO_LCD_WIDTH_MASK 0x03FF
@@ -250,11 +250,11 @@ static void __rotate_lcd(struct glamofb_handle *glamo, uint32_t rotation)
break;
}
- reg_set_bit_mask(glamo,
+ glamofb_reg_set_bit_mask(glamo,
GLAMO_REG_LCD_WIDTH,
GLAMO_LCD_ROT_MODE_MASK,
glamo_rot);
- reg_set_bit_mask(glamo,
+ glamofb_reg_set_bit_mask(glamo,
GLAMO_REG_LCD_MODE1,
GLAMO_LCD_MODE1_ROTATE_EN,
(glamo_rot != GLAMO_LCD_ROT_MODE_0) ?
@@ -264,7 +264,7 @@ static void __rotate_lcd(struct glamofb_handle *glamo, uint32_t rotation)
static inline int glamofb_cmdq_empty(struct glamofb_handle *gfb)
{
/* DGCMdQempty -- 1 == command queue is empty */
- return reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
+ return glamofb_reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
}
/* call holding gfb->lock_cmd when locking, until you unlock */
@@ -285,14 +285,14 @@ static int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
dev_dbg(gfb->dev, "empty!\n");
/* display the entire frame then switch to command */
- reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+ glamofb_reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
GLAMO_LCD_CMD_TYPE_DISP |
GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
/* wait until lcd idle */
dev_dbg(gfb->dev, "waiting for lcd idle: ");
timeout = 2000000;
- while (!(reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
+ while (!(glamofb_reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
(timeout--))
cpu_relax();
if (timeout < 0) {
@@ -308,12 +308,12 @@ static int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
} else {
/* RGB interface needs vsync/hsync */
- if (reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
- reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+ if (glamofb_reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
+ glamofb_reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
GLAMO_LCD_CMD_TYPE_DISP |
GLAMO_LCD_CMD_DATA_DISP_SYNC);
- reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+ glamofb_reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
GLAMO_LCD_CMD_TYPE_DISP |
GLAMO_LCD_CMD_DATA_DISP_FIRE);
}
@@ -339,15 +339,15 @@ static void glamofb_program_mode(struct glamofb_handle *gfb)
glamo_engine_reclock(gcore, GLAMO_ENGINE_LCD,
(1000000000UL / gfb->fb->var.pixclock) * 1000);
- reg_set_bit_mask(gfb,
+ glamofb_reg_set_bit_mask(gfb,
GLAMO_REG_LCD_WIDTH,
GLAMO_LCD_WIDTH_MASK,
var->xres);
- reg_set_bit_mask(gfb,
+ glamofb_reg_set_bit_mask(gfb,
GLAMO_REG_LCD_HEIGHT,
GLAMO_LCD_HEIGHT_MASK,
var->yres);
- reg_set_bit_mask(gfb,
+ glamofb_reg_set_bit_mask(gfb,
GLAMO_REG_LCD_PITCH,
GLAMO_LCD_PITCH_MASK,
gfb->fb->fix.line_length);
@@ -362,15 +362,15 @@ static void glamofb_program_mode(struct glamofb_handle *gfb)
fp = disp + var->xres;
total = fp + var->right_margin;
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_TOTAL,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_TOTAL,
GLAMO_LCD_HV_TOTAL_MASK, total);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_START,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_START,
GLAMO_LCD_HV_RETR_START_MASK, sync);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_END,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_END,
GLAMO_LCD_HV_RETR_END_MASK, bp);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_START,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_START,
GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_END,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_END,
GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
sync = 0;
@@ -379,15 +379,15 @@ static void glamofb_program_mode(struct glamofb_handle *gfb)
fp = disp + var->yres;
total = fp + var->lower_margin;
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_TOTAL,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_TOTAL,
GLAMO_LCD_HV_TOTAL_MASK, total);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_START,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_START,
GLAMO_LCD_HV_RETR_START_MASK, sync);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_END,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_END,
GLAMO_LCD_HV_RETR_END_MASK, bp);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_START,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_START,
GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
- reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_END,
+ glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_END,
GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
glamofb_cmd_mode(gfb, 0);
@@ -550,8 +550,8 @@ static inline void glamofb_vsync_wait(struct glamofb_handle *glamo, int line,
int count[2];
do {
- count[0] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
- count[1] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
+ count[0] = glamofb_reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
+ count[1] = glamofb_reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
} while (count[0] != count[1] ||
(line < count[0] + range &&
size > count[0] - range) ||
@@ -567,19 +567,19 @@ static void glamofb_cursor_onoff(struct glamofb_handle *glamo, int on)
int y, size;
if (glamo->cursor_on) {
- y = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
- size = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
+ y = glamofb_reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
+ size = glamofb_reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
glamofb_vsync_wait(glamo, y, size, 30);
}
- reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
+ glamofb_reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
GLAMO_LCD_MODE1_CURSOR_EN,
on ? GLAMO_LCD_MODE1_CURSOR_EN : 0);
glamo->cursor_on = on;
/* Hide the cursor by default */
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
}
static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
@@ -589,13 +589,13 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
spin_lock_irqsave(&glamo->lock_cmd, flags);
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
cursor->enable ? cursor->image.width : 0);
if (cursor->set & FB_CUR_SETPOS) {
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
cursor->image.dx);
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
cursor->image.dy);
}
@@ -603,13 +603,13 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
uint16_t fg = glamo->pseudo_pal[cursor->image.fg_color];
uint16_t bg = glamo->pseudo_pal[cursor->image.bg_color];
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
}
if (cursor->set & FB_CUR_SETHOT)
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
(cursor->hot.x << 8) | cursor->hot.y);
if ((cursor->set & FB_CUR_SETSIZE) ||
@@ -628,9 +628,9 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
}
pitch = ((cursor->image.width + 7) >> 2) & ~1;
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
pitch);
- reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
+ glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
cursor->image.height);
for (y = 0; y < cursor->image.height; y++) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 13:22:55 +0000