diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/irqs.h | 194 | ||||
| -rw-r--r-- | include/linux/glamo-gpio.h | 99 | ||||
| -rw-r--r-- | include/linux/glamofb.h | 39 | ||||
| -rw-r--r-- | include/linux/spi/glamo.h | 28 |
4 files changed, 360 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h new file mode 100644 index 00000000000..ea945ea0899 --- /dev/null +++ b/include/asm-arm/arch-s3c2410/irqs.h @@ -0,0 +1,194 @@ +/* linux/include/asm-arm/arch-s3c2410/irqs.h + * + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +#ifndef __ASM_ARM_IRQ_H +#error "Do not include this directly, instead #include <asm/irq.h>" +#endif + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + */ + +#define S3C2410_CPUIRQ_OFFSET (16) + +#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) + +/* main cpu interrupts */ +#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ +#define IRQ_EINT1 S3C2410_IRQ(1) +#define IRQ_EINT2 S3C2410_IRQ(2) +#define IRQ_EINT3 S3C2410_IRQ(3) +#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ +#define IRQ_EINT8t23 S3C2410_IRQ(5) +#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ +#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ +#define IRQ_BATT_FLT S3C2410_IRQ(7) +#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ +#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ +#define IRQ_TIMER0 S3C2410_IRQ(10) +#define IRQ_TIMER1 S3C2410_IRQ(11) +#define IRQ_TIMER2 S3C2410_IRQ(12) +#define IRQ_TIMER3 S3C2410_IRQ(13) +#define IRQ_TIMER4 S3C2410_IRQ(14) +#define IRQ_UART2 S3C2410_IRQ(15) +#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ +#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ +#define IRQ_DMA1 S3C2410_IRQ(18) +#define IRQ_DMA2 S3C2410_IRQ(19) +#define IRQ_DMA3 S3C2410_IRQ(20) +#define IRQ_SDI S3C2410_IRQ(21) +#define IRQ_SPI0 S3C2410_IRQ(22) +#define IRQ_UART1 S3C2410_IRQ(23) +#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ +#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ +#define IRQ_USBD S3C2410_IRQ(25) +#define IRQ_USBH S3C2410_IRQ(26) +#define IRQ_IIC S3C2410_IRQ(27) +#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ +#define IRQ_SPI1 S3C2410_IRQ(29) +#define IRQ_RTC S3C2410_IRQ(30) +#define IRQ_ADCPARENT S3C2410_IRQ(31) + +/* interrupts generated from the external interrupts sources */ +#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ +#define IRQ_EINT5 S3C2410_IRQ(33) +#define IRQ_EINT6 S3C2410_IRQ(34) +#define IRQ_EINT7 S3C2410_IRQ(35) +#define IRQ_EINT8 S3C2410_IRQ(36) +#define IRQ_EINT9 S3C2410_IRQ(37) +#define IRQ_EINT10 S3C2410_IRQ(38) +#define IRQ_EINT11 S3C2410_IRQ(39) +#define IRQ_EINT12 S3C2410_IRQ(40) +#define IRQ_EINT13 S3C2410_IRQ(41) +#define IRQ_EINT14 S3C2410_IRQ(42) +#define IRQ_EINT15 S3C2410_IRQ(43) +#define IRQ_EINT16 S3C2410_IRQ(44) +#define IRQ_EINT17 S3C2410_IRQ(45) +#define IRQ_EINT18 S3C2410_IRQ(46) +#define IRQ_EINT19 S3C2410_IRQ(47) +#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ +#define IRQ_EINT21 S3C2410_IRQ(49) +#define IRQ_EINT22 S3C2410_IRQ(50) +#define IRQ_EINT23 S3C2410_IRQ(51) + + +#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) + +#define IRQ_LCD_FIFO S3C2410_IRQ(52) +#define IRQ_LCD_FRAME S3C2410_IRQ(53) + +/* IRQs for the interal UARTs, and ADC + * these need to be ordered in number of appearance in the + * SUBSRC mask register +*/ + +#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) + +#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ +#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) +#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) + +#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ +#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) +#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) + +#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ +#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) +#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) + +#define IRQ_TC S3C2410_IRQSUB(9) +#define IRQ_ADC S3C2410_IRQSUB(10) + +/* extra irqs for s3c2412 */ + +#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) + +#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) +#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) + +/* extra irqs for s3c2440 */ + +#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ +#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ +#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) +#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) + +/* irqs for s3c2443 */ + +#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ +#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ +#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ +#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ +#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ + +#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) +#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) + +#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) + +/* UART3 */ +#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) +#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) +#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) + +#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) +#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) + +#ifdef CONFIG_CPU_S3C2443 +#define _NR_IRQS (IRQ_S3C2443_AC97+1) +#else +#define _NR_IRQS (IRQ_S3C2440_AC97+1) +#endif + +/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ +#define FIQ_START IRQ_EINT0 + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase IRQ_BOARD_END, but keep it + * within sensible limits. + */ +#define IRQ_BOARD_START _NR_IRQS +#define IRQ_BOARD_END (_NR_IRQS + 10) + +#if defined(CONFIG_MACH_NEO1973_GTA02) +#define NR_IRQS (IRQ_BOARD_END) +#else +#define NR_IRQS (IRQ_BOARD_START) +#endif + +/* Neo1973 GTA02 interrupts */ +#define NEO1973_GTA02_IRQ(x) (IRQ_BOARD_START + (x)) +#define IRQ_GLAMO(x) NEO1973_GTA02_IRQ(x) +#define IRQ_GLAMO_HOSTBUS IRQ_GLAMO(0) +#define IRQ_GLAMO_JPEG IRQ_GLAMO(1) +#define IRQ_GLAMO_MPEG IRQ_GLAMO(2) +#define IRQ_GLAMO_MPROC1 IRQ_GLAMO(3) +#define IRQ_GLAMO_MPROC0 IRQ_GLAMO(4) +#define IRQ_GLAMO_CMDQUEUE IRQ_GLAMO(5) +#define IRQ_GLAMO_2D IRQ_GLAMO(6) +#define IRQ_GLAMO_MMC IRQ_GLAMO(7) +#define IRQ_GLAMO_RISC IRQ_GLAMO(8) + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/include/linux/glamo-gpio.h b/include/linux/glamo-gpio.h new file mode 100644 index 00000000000..d00f7e95a2a --- /dev/null +++ b/include/linux/glamo-gpio.h @@ -0,0 +1,99 @@ +#ifndef __GLAMO_GPIO_H +#define __GLAMO_GPIO_H + +struct glamo_core; + +#define GLAMO_GPIO_BANKA 0x0000 +#define GLAMO_GPIO_BANKB 0x1000 +#define GLAMO_GPIO_BANKC 0x2000 +#define GLAMO_GPIO_BANKD 0x3000 + +#define GLAMO_GPIONO(bank, pin) ((bank & 0xf000) | ((pin & 0xf) << 8)) + +#define GLAMO_GPIO_F_IN 0x0010 +#define GLAMO_GPIO_F_OUT 0x0020 +#define GLAMO_GPIO_F_FUNC 0x0030 + +#define GLAMO_GPIO0 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 0) +#define GLAMO_GPIO0_INPUT (GLAMO_GPIO0 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO0_OUTPUT (GLAMO_GPIO0 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO0_HA20 (GLAMO_GPIO0 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO1 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 1) +#define GLAMO_GPIO1_INPUT (GLAMO_GPIO1 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO1_OUTPUT (GLAMO_GPIO1 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO1_HA21 (GLAMO_GPIO1 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO2 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 2) +#define GLAMO_GPIO2_INPUT (GLAMO_GPIO2 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO2_OUTPUT (GLAMO_GPIO2 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO2_HA22 (GLAMO_GPIO2 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO3 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 3) +#define GLAMO_GPIO3_INPUT (GLAMO_GPIO3 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO3_OUTPUT (GLAMO_GPIO3 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO3_HA23 (GLAMO_GPIO3 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO4 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 0) +#define GLAMO_GPIO4_INPUT (GLAMO_GPIO4 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO4_OUTPUT (GLAMO_GPIO4 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO4_nLCS0 (GLAMO_GPIO4 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO5 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 1) +#define GLAMO_GPIO5_INPUT (GLAMO_GPIO5 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO5_OUTPUT (GLAMO_GPIO5 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO5_nLCS1 (GLAMO_GPIO5 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO6 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 2) +#define GLAMO_GPIO6_INPUT (GLAMO_GPIO6 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO6_OUTPUT (GLAMO_GPIO6 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO6_LDCLK (GLAMO_GPIO6 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO7 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 3) +#define GLAMO_GPIO7_INPUT (GLAMO_GPIO7 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO7_OUTPUT (GLAMO_GPIO7 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO7_nLDE (GLAMO_GPIO7 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO8 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 0) +#define GLAMO_GPIO8_INPUT (GLAMO_GPIO8 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO8_OUTPUT (GLAMO_GPIO8 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO8_LD16 (GLAMO_GPIO8 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO9 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 1) +#define GLAMO_GPIO9_INPUT (GLAMO_GPIO9 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO9_OUTPUT (GLAMO_GPIO9 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO9_LD17 (GLAMO_GPIO9 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO10 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 2) +#define GLAMO_GPIO10_INPUT (GLAMO_GPIO10 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO10_OUTPUT (GLAMO_GPIO10 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO10_LSCK (GLAMO_GPIO10 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO11 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 3) +#define GLAMO_GPIO11_INPUT (GLAMO_GPIO11 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO11_OUTPUT (GLAMO_GPIO11 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO11_LSDA (GLAMO_GPIO11 | GLAMO_GPIO_F_FUNC) + +#define GLAMO_GPIO12 GLAMO_GPIONO(GLAMO_GPIO_BANKD, 0) +#define GLAMO_GPIO12_INPUT (GLAMO_GPIO12 | GLAMO_GPIO_F_IN) +#define GLAMO_GPIO12_OUTPUT (GLAMO_GPIO12 | GLAMO_GPIO_F_OUT) +#define GLAMO_GPIO12_LSA0 (GLAMO_GPIO12 | GLAMO_GPIO_F_FUNC) + + +#define REG_OF_GPIO(gpio) (((gpio & 0xf000) >> 12)*2 \ + + GLAMO_REG_GPIO_GEN1) +#define NUM_OF_GPIO(gpio) ((gpio & 0x0f00) >> 8) +#define GPIO_OUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 0)) +#define OUTPUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 4)) +#define INPUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 8)) +#define FUNC_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 12)) + +void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin, + unsigned int value); + +int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin); + +void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc); + + +#endif /* _GLAMO_GPIO */ diff --git a/include/linux/glamofb.h b/include/linux/glamofb.h new file mode 100644 index 00000000000..24742a28ffd --- /dev/null +++ b/include/linux/glamofb.h @@ -0,0 +1,39 @@ +#ifndef _LINUX_GLAMOFB_H +#define _LINUX_GLAMOFB_H + +#include <linux/spi/glamo.h> + +struct glamofb_val { + unsigned int defval; + unsigned int min; + unsigned int max; +}; + +struct glamo_core; + +struct glamofb_platform_data { + int width, height; + int pixclock; + int left_margin, right_margin; + int upper_margin, lower_margin; + int hsync_len, vsync_len; + int fb_mem_size; + + struct glamofb_val xres; + struct glamofb_val yres; + struct glamofb_val bpp; + + struct glamo_spi_info *spi_info; + struct glamo_spigpio_info *spigpio_info; + struct glamo_core *glamo; + + /* glamo mmc platform specific info */ + void (*glamo_set_mci_power)(unsigned char power_mode, + unsigned short vdd); + int (*glamo_irq_is_wired)(void); +}; + +void glamofb_cmd_mode(struct glamofb_handle *gfb, int on); +int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val); + +#endif diff --git a/include/linux/spi/glamo.h b/include/linux/spi/glamo.h new file mode 100644 index 00000000000..86419ea7dca --- /dev/null +++ b/include/linux/spi/glamo.h @@ -0,0 +1,28 @@ +#ifndef __GLAMO_SPI_H +#define __GLAMO_SPI_H + +#include <linux/glamo-gpio.h> + +struct spi_board_info; +struct glamofb_handle; +struct glamo_core; + +struct glamo_spi_info { + unsigned long board_size; + struct spi_board_info *board_info; + struct glamofb_handle *glamofb_handle; +}; + +struct glamo_spigpio_info { + unsigned int pin_clk; + unsigned int pin_mosi; + unsigned int pin_miso; + unsigned int pin_cs; + + unsigned int board_size; + struct spi_board_info *board_info; + struct glamo_core *glamo; +}; + + +#endif |