1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
|
/* arch/arm/plat-s3c64xx/irq-pm.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - Interrupt handling Power Management
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/regs-serial.h>
#include <plat/regs-timer.h>
#include <plat/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/pm.h>
/* We handled all the IRQ types in this code, to save having to make several
* small files to handle each different type separately. Having the EINT_GRP
* code here shouldn't be as much bloat as the IRQ table space needed when
* they are enabled. The added benefit is we ensure that these registers are
* in the same state as we suspended.
*/
static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C64XX_PRIORITY),
SAVE_ITEM(S3C64XX_EINT0CON0),
SAVE_ITEM(S3C64XX_EINT0CON1),
SAVE_ITEM(S3C64XX_EINT0FLTCON0),
SAVE_ITEM(S3C64XX_EINT0FLTCON1),
SAVE_ITEM(S3C64XX_EINT0FLTCON2),
SAVE_ITEM(S3C64XX_EINT0FLTCON3),
SAVE_ITEM(S3C64XX_EINT0MASK),
SAVE_ITEM(S3C64XX_TINT_CSTAT),
};
static struct irq_grp_save {
u32 fltcon;
u32 con;
u32 mask;
} eint_grp_save[5];
struct irq_vic_save {
u32 int_select;
u32 int_enable;
u32 soft_int;
u32 protect;
u32 vect_addr[32];
u32 vect_cntl[32];
};
static struct irq_vic_save irq_pm_vic0_save;
static struct irq_vic_save irq_pm_vic1_save;
static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save)
{
int v;
save->int_select = readl(base + VIC_INT_SELECT);
save->int_enable = readl(base + VIC_INT_ENABLE);
save->soft_int = readl(base + VIC_INT_SOFT);
save->protect = readl(base + VIC_PROTECT);
S3C_PMDBG("%s: select=%08x, enable=%08x, protect=%08x\n", __func__,
save->int_select, save->int_enable, save->protect);
for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4));
save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4));
}
}
static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save)
{
int v;
writel(save->int_select, base + VIC_INT_SELECT);
writel(save->protect, base + VIC_PROTECT);
/* set the enabled ints and then clear the non-enabled */
writel(save->int_enable, base + VIC_INT_ENABLE);
writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR);
/* and the same for the soft-int register */
writel(save->soft_int, base + VIC_INT_SOFT);
writel(~save->soft_int, base + VIC_INT_SOFT_CLEAR);
S3C_PMDBG("%s: vic int_enable=%08x\n", __func__, readl(base + VIC_INT_ENABLE));
for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4));
writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4));
}
}
static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
{
struct irq_grp_save *grp = eint_grp_save;
int i;
S3C_PMDBG("%s: suspending IRQs\n", __func__);
s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save);
s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save);
s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
}
return 0;
}
static int s3c64xx_irq_pm_resume(struct sys_device *dev)
{
struct irq_grp_save *grp = eint_grp_save;
int i;
S3C_PMDBG("%s: resuming IRQs\n", __func__);
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
s3c64xx_vic_restore(S3C_VA_VIC0, &irq_pm_vic0_save);
s3c64xx_vic_restore(S3C_VA_VIC1, &irq_pm_vic1_save);
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
__raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
__raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
__raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
}
S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
return 0;
}
static struct sysdev_driver s3c64xx_irq_driver = {
.suspend = s3c64xx_irq_pm_suspend,
.resume = s3c64xx_irq_pm_resume,
};
static int __init s3c64xx_irq_pm_init(void)
{
return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
}
arch_initcall(s3c64xx_irq_pm_init);
|
