blob: 6ef4b7867b1b356a933ebf1744e65739adc87838 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
#ifndef __ASM_SMP_H
#define __ASM_SMP_H
#if defined(CONFIG_SMP)
/* Page Zero Location PDC will look for the address to branch to when we poke
** slave CPUs still in "Icache loop".
*/
#define PDC_OS_BOOT_RENDEZVOUS 0x10
#define PDC_OS_BOOT_RENDEZVOUS_HI 0x28
#ifndef ASSEMBLY
#include <linux/bitops.h>
#include <linux/threads.h> /* for NR_CPUS */
#include <linux/cpumask.h>
typedef unsigned long address_t;
/*
* Private routines/data
*
* physical and logical are equivalent until we support CPU hotplug.
*/
#define cpu_number_map(cpu) (cpu)
#define cpu_logical_map(cpu) (cpu)
extern void smp_send_reschedule(int cpu);
extern void smp_send_all_nop(void);
extern void arch_send_call_function_single_ipi(int cpu);
extern void arch_send_call_function_ipi(cpumask_t mask);
#endif /* !ASSEMBLY */
/*
* This magic constant controls our willingness to transfer
* a process across CPUs. Such a transfer incurs cache and tlb
* misses. The current value is inherited from i386. Still needs
* to be tuned for parisc.
*/
#define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
#define raw_smp_processor_id() (current_thread_info()->cpu)
#else /* CONFIG_SMP */
static inline void smp_send_all_nop(void) { return; }
#endif
#define NO_PROC_ID 0xFF /* No processor magic marker */
#define ANY_PROC_ID 0xFF /* Any processor magic marker */
static inline int __cpu_disable (void) {
return 0;
}
static inline void __cpu_die (unsigned int cpu) {
while(1)
;
}
extern int __cpu_up (unsigned int cpu);
#endif /* __ASM_SMP_H */
|
