aboutsummaryrefslogtreecommitdiff
path: root/drivers/media/video/cx18/cx18-io.h
blob: 287a5e8bf67b8a988c88b4bb0cdb7315c2d3b613 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
/*
 *  cx18 driver PCI memory mapped IO access routines
 *
 *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
 *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
 *  02111-1307  USA
 */

#ifndef CX18_IO_H
#define CX18_IO_H

#include "cx18-driver.h"

static inline void cx18_io_delay(struct cx18 *cx)
{
	if (cx->options.mmio_ndelay)
		ndelay(cx->options.mmio_ndelay);
}

/*
 * Readback and retry of MMIO access for reliability:
 * The concept was suggested by Steve Toth <stoth@linuxtv.org>.
 * The implmentation is the fault of Andy Walls <awalls@radix.net>.
 */

/* Statistics gathering */
static inline
void cx18_log_write_retries(struct cx18 *cx, int i, const void __iomem *addr)
{
	if (i > CX18_MAX_MMIO_RETRIES)
		i = CX18_MAX_MMIO_RETRIES;
	atomic_inc(&cx->mmio_stats.retried_write[i]);
	return;
}

static inline
void cx18_log_read_retries(struct cx18 *cx, int i, const void __iomem *addr)
{
	if (i > CX18_MAX_MMIO_RETRIES)
		i = CX18_MAX_MMIO_RETRIES;
	atomic_inc(&cx->mmio_stats.retried_read[i]);
	return;
}

void cx18_log_statistics(struct cx18 *cx);

/* Non byteswapping memory mapped IO */
static inline
void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
{
	__raw_writel(val, addr);
	cx18_io_delay(cx);
}

void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);

static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
{
	if (cx18_retry_mmio)
		cx18_raw_writel_retry(cx, val, addr);
	else
		cx18_raw_writel_noretry(cx, val, addr);
}


static inline
u32 cx18_raw_readl_noretry(struct cx18 *cx, const void __iomem *addr)
{
	u32 ret = __raw_readl(addr);
	cx18_io_delay(cx);
	return ret;
}

u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr);

static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
{
	if (cx18_retry_mmio)
		return cx18_raw_readl_retry(cx, addr);

	return cx18_raw_readl_noretry(cx, addr);
}


static inline
u16 cx18_raw_readw_noretry(struct cx18 *cx, const void __iomem *addr)
{
	u16 ret = __raw_readw(addr);
	cx18_io_delay(cx);
	return ret;
}

u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr);

static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
{
	if (cx18_retry_mmio)
		return cx18_raw_readw_retry(cx, addr);

	return cx18_raw_readw_noretry(cx, addr);
}


/* Normal memory mapped IO */
static inline
void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
{
	writel(val, addr);
	cx18_io_delay(cx);
}

void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);

static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
{
	if (cx18_retry_mmio)
		cx18_writel_retry(cx, val, addr);
	else
		cx18_writel_noretry(cx, val, addr);
}


static inline
void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
{
	writew(val, addr);
	cx18_io_delay(cx);
}

void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr);

static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
{
	if (cx18_retry_mmio)
		cx18_writew_retry(cx, val, addr);
	else
		cx18_writew_noretry(cx, val, addr);
}


static inline
void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
{
	writeb(val, addr);
	cx18_io_delay(cx);
}

void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr);

static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
{
	if (cx18_retry_mmio)
		cx18_writeb_retry(cx, val, addr);
	else
		cx18_writeb_noretry(cx, val, addr);
}


static inline u32 cx18_readl_noretry(struct cx18 *cx, const void __iomem *addr)
{
	u32 ret = readl(addr);
	cx18_io_delay(cx);
	return ret;
}

u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr);

static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
{
	if (cx18_retry_mmio)
		return cx18_readl_retry(cx, addr);

	return cx18_readl_noretry(cx, addr);
}


static inline u16 cx18_readw_noretry(struct cx18 *cx, const void __iomem *addr)
{
	u16 ret = readw(addr);
	cx18_io_delay(cx);
	return ret;
}

u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr);

static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
{
	if (cx18_retry_mmio)
		return cx18_readw_retry(cx, addr);

	return cx18_readw_noretry(cx, addr);
}


static inline u8 cx18_readb_noretry(struct cx18 *cx, const void __iomem *addr)
{
	u8 ret = readb(addr);
	cx18_io_delay(cx);
	return ret;
}

u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr);

static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
{
	if (cx18_retry_mmio)
		return cx18_readb_retry(cx, addr);

	return cx18_readb_noretry(cx, addr);
}


static inline
u32 cx18_write_sync_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
{
	cx18_writel_noretry(cx, val, addr);
	return cx18_readl_noretry(cx, addr);
}

static inline
u32 cx18_write_sync_retry(struct cx18 *cx, u32 val, void __iomem *addr)
{
	cx18_writel_retry(cx, val, addr);
	return cx18_readl_retry(cx, addr);
}

static inline u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
{
	if (cx18_retry_mmio)
		return cx18_write_sync_retry(cx, val, addr);

	return cx18_write_sync_noretry(cx, val, addr);
}


void cx18_memcpy_fromio(struct cx18 *cx, void *to,
			const void __iomem *from, unsigned int len);
void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);


/* Access "register" region of CX23418 memory mapped I/O */
static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
{
	cx18_writel_noretry(cx, val, cx->reg_mem + reg);
}

static inline void cx18_write_reg_retry(struct cx18 *cx, u32 val, u32 reg)
{
	cx18_writel_retry(cx, val, cx->reg_mem + reg);
}

static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
{
	if (cx18_retry_mmio)
		cx18_write_reg_retry(cx, val, reg);
	else
		cx18_write_reg_noretry(cx, val, reg);
}


static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg)
{
	return cx18_readl_noretry(cx, cx->reg_mem + reg);
}

static inline u32 cx18_read_reg_retry(struct cx18 *cx, u32 reg)
{
	return cx18_readl_retry(cx, cx->reg_mem + reg);
}

static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
{
	if (cx18_retry_mmio)
		return cx18_read_reg_retry(cx, reg);

	return cx18_read_reg_noretry(cx, reg);
}


static inline u32 cx18_write_reg_sync_noretry(struct cx18 *cx, u32 val, u32 reg)
{
	return cx18_write_sync_noretry(cx, val, cx->reg_mem + reg);
}

static inline u32 cx18_write_reg_sync_retry(struct cx18 *cx, u32 val, u32 reg)
{
	return cx18_write_sync_retry(cx, val, cx->reg_mem + reg);
}

static inline u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
{
	if (cx18_retry_mmio)
		return cx18_write_reg_sync_retry(cx, val, reg);

	return cx18_write_reg_sync_noretry(cx, val, reg);
}


/* Access "encoder memory" region of CX23418 memory mapped I/O */
static inline void cx18_write_enc_noretry(struct cx18 *cx, u32 val, u32 addr)
{
	cx18_writel_noretry(cx, val, cx->enc_mem + addr);
}

static inline void cx18_write_enc_retry(struct cx18 *cx, u32 val, u32 addr)
{
	cx18_writel_retry(cx, val, cx->enc_mem + addr);
}

static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
{
	if (cx18_retry_mmio)
		cx18_write_enc_retry(cx, val, addr);
	else
		cx18_write_enc_noretry(cx, val, addr);
}


static inline u32 cx18_read_enc_noretry(struct cx18 *cx, u32 addr)
{
	return cx18_readl_noretry(cx, cx->enc_mem + addr);
}

static inline u32 cx18_read_enc_retry(struct cx18 *cx, u32 addr)
{
	return cx18_readl_retry(cx, cx->enc_mem + addr);
}

static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
{
	if (cx18_retry_mmio)
		return cx18_read_enc_retry(cx, addr);

	return cx18_read_enc_noretry(cx, addr);
}

static inline
u32 cx18_write_enc_sync_noretry(struct cx18 *cx, u32 val, u32 addr)
{
	return cx18_write_sync_noretry(cx, val, cx->enc_mem + addr);
}

static inline
u32 cx18_write_enc_sync_retry(struct cx18 *cx, u32 val, u32 addr)
{
	return cx18_write_sync_retry(cx, val, cx->enc_mem + addr);
}

static inline
u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
{
	if (cx18_retry_mmio)
		return cx18_write_enc_sync_retry(cx, val, addr);

	return cx18_write_enc_sync_noretry(cx, val, addr);
}

void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
void cx18_setup_page(struct cx18 *cx, u32 addr);

#endif /* CX18_IO_H */